M69KB128AA datasheet(18/68 Pages) STMICROELECTRONICS

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6 Synchronous operating modes

M69KB128AA

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Synchronous operating modes

The synchronous modes allow high-speed read and write operations synchronized with the

clock. Refresh cycles are indicated to the host system by asserting the WAIT signal that, in

turn, stalls the microcontroller.

The M69KB128AA supports two types of synchronous modes:

●

NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode Flash

memory microcontrollers.

●

Full Synchronous: both read and write are performed in Synchronous mode.

All the options related to the synchronous modes can be configured through the Bus

Configuration Register, BCR. In particular, the device is put in Synchronous mode, either NOR-

Flash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to ‘0’.

The device will automatically detect whether the NOR-Flash or the Full Synchronous mode is

being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of the

Clock K is detected while L is held Low, VIL (active), the device operates in Full Synchronous

mode.

6.1

NOR-Flash Synchronous mode

In this mode, the device operates in synchronous mode for read operations, and in

asynchronous mode for write operations.

Asynchronous write operations are performed at Word level, with LB and UB Low. The data is

latched on E, W, LB, UB, whichever occurs first. RCR and BCR registers can be programmed in

NOR-Flash Asynchronous Write mode, using the CR controlled method (see Section 7.1:

Programming the Registers by the CR controlled method). A Program Configuration Register

operation can only be issued if the device is in idle state and no burst operations are in

progress. NOR-Flash Asynchronous Write operations are described in Table 5: Asynchronous

Write Operations (NOR-Flash Synchronous mode).

Synchronous read operations are also performed at Word level. They are controlled by the

state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The

initial Burst Read access latches the Burst start address. The number of Words to be output is

controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock cycles,

also called Latency. NOR-Flash Synchronous Burst Read operations are described in Table 6:

Synchronous Read Operations (NOR-Flash Synchronous mode).

When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full

Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns.

However, when it is not possible to meet these specifications, special care must be taken to

keep addresses stable after driving the Write Enable signal, W, Low.

Write operations are considered as Asynchronous operations until the device detects a valid

clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5:

Switching from Asynchronous to Synchronous Write operation).

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