M69KB128AA datasheet(59/68 Pages) STMICROELECTRONICS

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M69KB128AA

9 DC and AC parameters

59/68

Table 22.

Synchronous Burst Write AC Characteristics

Symbol

Alt.

Parameter(1)

These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement

Conditions and Figure 13: AC Measurement Load Circuit.

M69KB128AA

Unit

104MHz

80MHz

66MHz

Min

Max

Min

Max

Min

Max

tAVWL

tLLWL

(2)

tAVWL and tLLWL, are required if tELKH> 20ns.

tAS

Address Set-up to Beginning of Write

Operation

tAVKH

tDVKH

tWLKH

tLLKH

tBLKH

tWHKH

tWHWL

tSP

Set-up Time to Active Clock Edge

tEHEL

(3)

A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge

of K; or if E is High for longer than 15ns.

tCBPH

Chip Enable High between Subsequent

Operations in Full-Synchronous or

NOR-Flash mode.

tELEH

(3)

tCEM

Maximum Chip Enable Low Pulse

µs

tELTV

tLLTV

tCEW Chip Enable Low to WAIT Valid

7.5

tELKH

tCSP

Chip Enable Low to Clock High

tKHAX

tKHRL

tKHLH

tKHDX

tKHEH

tKHBH

tKHWH

tHD

Hold Time From Active Clock Edge

tKHLL

tKADV

Last Clock Rising Edge to Latch Enable

Low (Fixed Latency)

tEHDZ

tEHTZ

(4)

The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.

tHZ

Chip Enable High to Input Hi-Z or WAIT

Hi-Z

tKHTV

tKHTX

tKHTL Clock High to WAIT Valid or Low

tLHAX

tAVH

Latch Enable High to Address Transition

(Fixed Latency)

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