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STM32F103C8 数据表(PDF) 56 Page - STMicroelectronics

部件名 STM32F103C8
功能描述  Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces
PDF  67 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F103C8 数据表(HTML) 56 Page - STMicroelectronics

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Electrical characteristics
STM32F103xx
56/67
Figure 23.
ADC accuracy characteristics
Figure 24.
Typical connection diagram using the ADC
1.
Refer to Table 39 for the values of RADC and CADC.
2.
CPARASITIC must be added to CAIN. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high CPARASITIC value will downgrade conversion
accuracy. To remedy this, fADC should be reduced.
EO
EG
1LSBIDEAL
1LSB
IDEAL
V
DDA
V
SSA
1024
-----------------------------------------
=
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1023
1022
1021
5
4
3
2
1
0
7
6
1
2
3
456
7
1021 1022 1023 1024
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395
ai14150
STM32F103xx
VDD
AINx
IL±1mA
0.6V
VT
RAIN
CAIN(1)
VAIN
0.6V
VT
RADC
12-bit A/D
conversion
CADC



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