STM32F103C8 datasheet(10/67 Pages) STMICROELECTRONICS

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Description

STM32F103xx

10/67

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

●

MR is used in the nominal regulation mode (Run)

●

LPR is used in the Stop modes.

●

Power down is used in Standby Mode: the regulator output is in high impedance: the

kernel circuitry is powered-down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby Mode, providing high

impedance output.

Low-power modes

The STM32F103xx performance line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

●

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

●

Stop mode

Stop mode allows to achieve the lowest power consumption while retaining the content

of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI

and the HSE RC oscillators are disabled. The voltage regulator can also be put either in

normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

●

Standby mode

The Standby mode allows to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI and the HSE RC oscillators are also switched off. After entering Standby

mode, SRAM and registers content are lost except for registers in the Backup domain

and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note:

The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose and

advanced control timers TIMx and ADC.

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