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KSZ9567R 数据表(PDF) 177 Page - Microchip Technology |
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KSZ9567R 数据表(HTML) 177 Page - Microchip Technology |
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177 / 233 page  2022 Microchip Technology Inc. and its subsidiaries DS00002329E-page 177 KSZ9567R 5.2.8 PORT N: PORT SWITCH EGRESS CONTROL REGISTERS (0xN900 - 0xN9FF) 5.2.8.1 Port Transmit Queue Index Register This register holds an index value that is used when accessing several registers that follow. This register may be accessed as an 8-bit register, with bits [7:0] located at address 0xN903. 5.2.8.2 Port Transmit Queue PVID Register This register may be accessed as an 8-bit register, with bits [7:0] located at address 0xN903. 28 YR Drop Disable 1 = Drop YELLOW/RED is disabled 0 = Drop YELLOW/RED is enabled R/W 0b 27 R Drop Disable 1 = Drop RED is disabled 0 = Drop RED is enabled R/W 0b 26 Drop All 1 = Drop all packets wile the max threshold is exceeded 0 = Drop based on WRED Queue Probability Multiplier R/W 0b 25:24 RESERVED RO 00b 23:0 Packet Event Counter Packer event count for the connection from the Queue Pointer of the port pointed to by the Port index. R 0x00000 Address: 0xN900 - 0xN903 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:2 RESERVED RO 0x00000000 1:0 Queue Index Points to the queue number for subsequent queue configuration registers. R/W 00 Address: 0xN904 - 0x907 Port N: 1-7 Size: 32 bits Bits Description Type Default 31:1 RESERVED RO 0x00000000 0 Port VID Replacement 1 = For any egress packet with a non-zero VLAN ID, replace the VID with the port default VID from the Port Default Tag 0 Register and Port Default Tag 1 Register. If double tagging is enabled, it is the ISP tag ID that will be replaced. 0 = Do not replace the VID. R/W 0b Bits Description Type Default |
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