KSZ9567R datasheet(181/233 Pages) MICROCHIP

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DS00002329E-page 181

KSZ9567R

5.2.9.3

Port Transmit Queue Memory Register

5.2.10

PORT N: PORT SWITCH ADDRESS LOOKUP CONTROL REGISTERS (0xNB00 - 0xNBFF)

5.2.10.1

Port Control 2 Register

Address:

0xNA10 - 0xNA13

Port N: 1-3

Size:

32 bits

Bits

Description

Type

Default

31:11

RESERVED

0x000000

10:0

Port N Transmit Queue Blocks Used (TXQBU)

Real-time number of memory blocks used for the transmit queue(s) of port N.

The default value corresponds to when no packets are queued to transmit

out the particular port.

0x000

Address:

0xNB00

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

Null VID Lookup Enable

How to handle tagged packets with VID = 0.

1 = Non-standard operation. VLAN Table lookup using VID = 0.

0 = Standard operation. VLAN Table lookup using the port default VID (Port

Default Tag 0 Register and Port Default Tag 1 Register)

R/W

Ingress VLAN Filtering

1 = Discard packets whose VID port membership in the VLAN Table does

not include the ingress port

0 = No ingress filtering

R/W

Discard Non-PVID Packet

1 = Discard packets whose VID does not match the ingress port default VID

0 = Do not compare VID to the port default VID

R/W

MAC Based 802.1X Enable

1 = Enable MAC based 802.1X authentication in lookup engine

0 = Only use ACL (if enabled) to perform MAC based authentication

R/W

Self-Address Filtering – Port Enable

The source address of received packets is compared to the MAC address in

the Switch MAC Address 0 Register through Switch MAC Address 5

Both this port enable bit and the global enable bit in the Switch Lookup

Engine Control 1 Register must be set to enable self-address filtering.

1 = Enable self-address filtering for this port.

0 = Disable self-address filtering for this port.

R/W

RESERVED

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