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ST10F272M 数据表(PDF) 152 Page - STMicroelectronics |
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ST10F272M 数据表(HTML) 152 Page - STMicroelectronics |
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152 / 175 page  Electrical characteristics ST10F272M 152/176 t17 SR Address/Unlatched CS to valid data in – 20 + 2tA + + tC – 4TCL – 30 + + 2tA + tC ns t18 SR Data hold after RD rising edge 0– 0 – ns t19 SR Data float after RD1 – 16.5 + tF – 2TCL – 8.5 + tF ns t22 CC Data valid to WR 10 + tC – 2TCL – 15 + tC –ns t23 CC Data hold after WR 4 + tF – 2TCL – 8.5 + tF –ns t25 CC ALE rising edge after RD, WR 15 + tF – 2TCL – 10 + tF –ns t27 CC Address/Unlatched CS hold after RD, WR 10 + tF – 2TCL – 15 + tF –ns t38 CC ALE falling edge to Latched CS – 4 – tA 10 – tA – 4 – tA 10 – tA ns t39 SR Latched CS low to Valid Data In – 16.5 + tC + + 2tA – 3TCL - 21 + + tC + 2tA ns t40 CC Latched CS hold after RD, WR 27 + tF – 3TCL - 10.5 + tF –ns t42 CC ALE fall. edge to RdCS, WrCS (with RW delay) 7 + tA – TCL - 5.5 + tA –ns t43 CC ALE fall. edge to RdCS, WrCS (no RW delay) -5.5 + tA – -5.5 + tA –ns t44 CC Address float after RdCS, WrCS (with RW delay)1 – 1.5 – 1.5 ns t45 CC Address float after RdCS, WrCS (no RW delay)1 – 14 – TCL + 1.5 ns t46 SR RdCS to Valid Data In (with RW delay) –4 + tC –2TCL - 21 + tC ns t47 SR RdCS to Valid Data In (no RW delay) – 16.5 + tC –3TCL - 21 + tC ns t48 CC RdCS, WrCS Low Time (with RW delay) 15.5 + tC – 2TCL - 9.5 + tC –ns t49 CC RdCS, WrCS Low Time (no RW delay) 28 + tC – 3TCL - 9.5 + tC –ns t50 CC Data valid to WrCS 10 + tC – 2TCL - 15 + tC –ns t51 SR Data hold after RdCS 0– 0 – ns t52 SR Data float after RdCS1 – 16.5 + tF – 2TCL - 8.5 + tF ns t54 CC Address hold after RdCS, WrCS 6 + tF – 2TCL - 19 + tF –ns t56 CC Data hold after WrCS 6 + tF – 2TCL - 19 + tF –ns Table 70. Multiplexed bus timings (continued) Symbol Parameter fCPU = 40 MHz TCL = 12.5ns Variable CPU clock 1/2 TCL = 1 to 40 MHz Unit Min Max Min Max |
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