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ST10F272M 数据表(PDF) 151 Page - STMicroelectronics

部件名 ST10F272M
功能描述  16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
PDF  175 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST10F272M 数据表(HTML) 151 Page - STMicroelectronics

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Electrical characteristics
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24.8.15
External memory bus timing
The following sections include the External Memory Bus timings. The given values are
computed for a maximum CPU clock of 40 MHz.
Note:
All External Memory Bus Timings and SSC Timings listed in the following tables are granted
by Design Characterization and not fully tested in production.
24.8.16
Multiplexed bus
VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF,
ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40 MHz CPU clock without wait states)
Table 69.
Memory cycle variables
Description
Symbol
Values
ALE Extension
tA
TCL x [ALECTL]
Memory Cycle Time wait states
tC
2TCL x (15 - [MCTC])
Memory Tri-state Time
tF
2TCL x (1 - [MTTC])
Table 70.
Multiplexed bus timings
Symbol
Parameter
fCPU = 40 MHz
TCL = 12.5ns
Variable CPU clock
1/2 TCL = 1 to 40 MHz
Unit
Min
Max
Min
Max
t5
CC
ALE high time
4 + tA
TCL – 8.5 + tA
–ns
t6
CC
Address setup to ALE
1.5 + tA
TCL – 11 + tA
–ns
t7
CC
Address hold after ALE
4 + tA
TCL – 8.5 + tA
–ns
t8
tCC
ALE falling edge to RD, WR
(with RW-delay)
4 + tA
TCL – 8.5 + tA
–ns
t9
CC
ALE falling edge to RD, WR
(no RW-delay)
– 8.5 + tA
– 8.5 + tA
–ns
t10 CC
Address float after RD, WR (with
RW-delay)1
–6
6
ns
t11 CC
Address float after RD, WR
(no RW-delay)1
18.5
TCL + 6
ns
t12 CC
RD, WR low time
(with RW-delay)
15.5 + tC
2TCL – 9.5 + tC
–ns
t13 CC
RD, WR low time
(no RW-delay)
28 + tC
3TCL – 9.5 + tC
–ns
t14 SR
RD to valid data in
(with RW-delay)
–6 + tC
2TCL – 19 + tC
ns
t15 SR
RD to valid data in
(no RW-delay)
18.5 + tC
3TCL – 19 + tC
ns
t16 SR ALE low to valid data in
17.5 +
+ tA + tC
3TCL – 20 +
+ tA + tC
ns



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