ST10F272M datasheet(147/175 Pages) STMICROELECTRONICS

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ST10F272M

Electrical characteristics

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Figure 46.

ST10F272M PLL jitter

24.8.10

PLL lock / unlock

During normal operation, if the PLL gets unlocked for any reason, an interrupt request to the

CPU is generated, and the reference clock (oscillator) is automatically disconnected from

the PLL input: in this way, the PLL goes into free-running mode, providing the system with a

backup clock signal (free running frequency ffree). This feature allows recovery from a crystal

failure occurrence without risking to go into an undefined configuration: The system is

provided with a clock allowing the execution of the PLL unlock interrupt routine in a safe

mode.

The path between reference clock and PLL input can be restored only by a hardware reset,

or by a bidirectional software or watchdog reset event that forces the RSTIN pin low.

Note:

The external RC circuit on RSTIN pin must be properly sized in order to extend the duration

of the low pulse to lock the PLL before the level at RSTIN pin is recognized high: A

bidirectional reset internally drives the RSTIN pin low for just 1024 TCL (definitly not

sufficient to lock the PLL starting from free-running mode).

N (CPU clock periods)

200

400

±5

±1

800

600

1000

1200

1400

64MHz

±2

±3

±4

24MHz

40MHz

32MHz

16MHz

TJIT

Table 63.

PLL characteristics (VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

tPSUP

PLL Start-up time(1)

Not 100% tested, guaranteed by design characterization

Stable VDD and reference clock

–

300

µs

tLOCK

PLL Lock-in time

Stable VDD and reference clock,

starting from free-running mode

–

250

µs

TJIT

Single Period Jitter(1)

(cycle to cycle = 2 TCL)

6 sigma time period variation

(peak to peak)

-500

+500

ffree

PLL free running frequency

Multiplication factors: 3, 4

250

2000

kHz

Multiplication factors: 5, 8, 10, 16

500

4000

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