ST10F272M datasheet(146/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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Jitter in the input clock

PLL acts like a low pass filter for any jitter in the input clock. Input Clock jitter with the

frequencies within the PLL loop bandwidth is passed to the PLL output and higher frequency

jitter (frequency > PLL bandwidth) is attenuated @20dB/decade.

Noise in the PLL loop

This contribution again can be caused by the following sources:

●

Device noise of the circuit in the PLL

●

Noise in supply and substrate.

Device noise of the circuit in the PLL

The long term jitter is inversely proportional to the bandwidth of the PLL: the wider the loop

bandwidth is, the lower the jitter is due to noise in the loop. Moreover, the long term jitter is

practically independent of the multiplication factor.

The most noise sensitive circuit in the PLL circuit is definitively the VCO (Voltage Controlled

Oscillator). There are two main sources of noise: thermal (random noise, frequency-

independent noise, thus, practically white noise) and flicker (low frequency noise, 1/f). For

the frequency characteristics of the VCO circuitry, the effect of the thermal noise results in a

1/f2 region in the output noise spectrum, while the flicker noise in a 1/f3. Assuming a

noiseless PLL input and supposing that the VCO is dominated by its 1/f2 noise, the R.M.S.

value of the accumulated jitter is proportional to the square root of N, where N is the number

of clock periods within the considered time interval.

On the contrary, assuming again a noiseless PLL input and supposing that the VCO is

dominated by its 1/f3 noise, the R.M.S. value of the accumulated jitter is proportional to N,

where N is the number of clock periods within the considered time interval.

The jitter in the PLL loop can be modelized as dominated by the i1/f2 noise for N smaller

than a certain value depending on the PLL output frequency and on the bandwidth

characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f3 noise

component. Lastly, for N greater than a second value of N, a saturation effect is evident, so

the jitter does not grow anymore when considering a longer time interval (jitter stable

increasing the number of clock periods N). The PLL loop acts as a high pass filter for any

noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation

value corresponds to what has been called self referred long term jitter of the PLL. In

Figure 46 the maximum jitter trend versus the number of clock periods N (for some typical

CPU frequencies) is shown: The curves represent the very worst case, computed taking into

account all corners of temperature, power supply and process variations: The real jitter is

always measured well below the given worst case values.

Noise in supply and substrate

Digital supply noise adds deterministic components to the PLL output jitter, independent of

the multiplication factor. Its effects are strongly reduced thanks to the particular care used in

the physical implementation and integration of the PLL module inside the device.

Nonetheless, the contribution of the digital noise to the global jitter is widely taken into

account in the curves provided in Figure 46.

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