ST10F272M datasheet(142/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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Figure 45.

Generation mechanisms for the CPU clock

24.8.3

Clock generation modes

The next Table 61 associates the combinations of these three bits with the respective clock

generation mode.

TCLTCL

fCPU

fXTAL

fCPU

fXTAL

Phase locked loop operation

Direct Clock Drive

TCL

fCPU

fXTAL

Prescaler Operation

Table 61.

On-chip clock generator selections

P0.15-13

(P0H.7-5)

CPU frequency

fCPU = fXTAL x F

External clock

input range(1)(3)

The external clock input range refers to a CPU clock range of 1...40 MHz. Moreover, the PLL usage is

limited to 4-8 MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock

through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced

through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no

crystal or resonator can be used).

Notes

fXTAL x 4

4 to 8 MHz

Default configuration

fXTAL x 3

5.3 to 8 MHz

fXTAL x 8

4 to 8 MHz

fXTAL x 5

6.4 to 8 MHz

fXTAL x 1

1 to 64 MHz

Direct Drive (oscillator bypassed)(2)

The maximum depends on the duty cycle of the external clock signal: when 40 MHz is used, 50% duty

cycle is granted (low phase = high phase = 12.5ns); when 20 MHz is selected a 25% duty cycle can be

accepted (minimum phase, high or low, again equal to 12.5ns).

fXTAL x 10

4 to 6.4 MHz

fXTAL / 2

4 to 8 MHz

CPU clock via prescaler(3)

The limits on input frequency are 4-8 MHz since the usage of the internal oscillator amplifier is required.

Also when the PLL is not used and the CPU clock corresponds to fXTAL/2, an external crystal or resonator

must be used: It is not possible to force any clock though an external clock source.

fXTAL x 16

4 MHz

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