ST10F272M datasheet(144/175 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F272M

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an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock

cycles).

The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator

watchdog Interrupt Request is flagged. The CPU clock will not switch back to the external

clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or

bidirectional Software / Watchdog reset) can switch the CPU clock source back to direct

clock input.

When the OWD is disabled, the CPU clock is always the external oscillator clock (in Direct

Drive or Prescaler Operation) and the PLL is switched off to decrease consumption supply

current.

24.8.7

Phase Locked Loop (PLL)

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked

loop is enabled and it provides the CPU clock (see Table 61). The PLL multiplies the input

frequency by the factor F which is selected via the combination of pins P0.15-13 (fCPU =

fXTAL x F). With every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to

the input clock. This synchronization is done smoothly, so the CPU clock frequency does not

change abruptly.

Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is

locked to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of

individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated

using the minimum TCL that is possible under the respective circumstances.

The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to

keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to

one TCL period.

This is especially important for bus cycles using wait states and for example, such as for the

operation of timers or serial interfaces. For all slower operations and longer periods (for

example, pulse train generation or measurement, or lower baudrates) the deviation caused

by the PLL jitter is negligible. Refer to next Section 24.8.9: PLL jitter for more details.

24.8.8

Voltage controlled oscillator

The ST10F272M implements a PLL which combines different levels of frequency dividers

with a Voltage Controlled Oscillator (VCO) working as frequency multiplier. The following

table gives a detailed summary of the internal settings and VCO frequency.

Table 62.

Internal PLL divider mechanism

P0.15-13

(P0H.7-5)

XTAL frequency

Input

prescaler

PLL

Output

prescaler

CPU frequency

fCPU = fXTAL x F

Multiply by

Divide by

4 to 8 MHz

fXTAL / 4

–

fXTAL x 4

5.3 to 10.6 MHz(1)

fXTAL / 4

–

fXTAL x 3

4 to 8 MHz

fXTAL / 4

–

fXTAL x 8

6.4 to 8 MHz(1)

fXTAL / 4

–

fXTAL x 5

1 to 40 MHz

–

PLL bypassed

–

fXTAL x 1

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