ST10F272M datasheet(145/175 Pages) STMICROELECTRONICS

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ST10F272M

Electrical characteristics

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Example 1

●

fXTAL = 4 MHz

●

P0(15:13) = ‘110’ (multiplication by 3)

●

PLL input frequency = 1 MHz

●

VCO frequency = 48 MHz: NOT VALID, must be 64 to 128 MHz

●

fCPU = NOT VALID

Example 2

●

fXTAL = 8 MHz

●

P0(15:13) = ‘100’ (multiplication by 5)

●

PLL input frequency = 2 MHz

●

VCO frequency = 80 MHz

●

PLL output frequency = 40 MHz (VCO frequency divided by 2)

●

fCPU = 40 MHz (no effect of Output Prescaler)

24.8.9

PLL jitter

The following terminology is hereafter defined:

●

Self referred single period jitter

Also called “Period Jitter”, it can be defined as the difference of the Tmax and Tmin,

where Tmax is maximum time period of the PLL output clock and Tmin is the minimum

time period of the PLL output clock.

●

Self referred long term jitter

Also called “N period jitter”, it can be defined as the difference of Tmax and Tmin, where

Tmax is the maximum time difference between N+1 clock rising edges and Tmin is the

minimum time difference between N+1 clock rising edges. Here N should be kept

sufficiently large to have the long term jitter. For N=1, this becomes the single period

jitter.

Jitter at the PLL output can be due to the following reasons:

●

Jitter in the input clock

●

Noise in the PLL loop

4 MHz

fXTAL / 2

–

fXTAL x 10

4 to 8 MHz(1)

–

PLL bypassed

fPLL / 2

fXTAL / 2

–

The PLL input frequency range is limited to 1 to 3.5 MHz, while the VCO oscillation range is 64 to 128 MHz. The CPU clock

frequency range when PLL is used is 16 to 40 MHz.

Table 62.

Internal PLL divider mechanism (continued)

P0.15-13

(P0H.7-5)

XTAL frequency

Input

prescaler

PLL

Output

prescaler

CPU frequency

fCPU = fXTAL x F

Multiply by

Divide by

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