AD4058BCPZ-R2 datasheet(30/66 Pages) AD

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Data Sheet

AD4052/AD4058

MODES OF OPERATION

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Rev. B | 30 of 66

SAMPLE MODE

In sample mode, a rising edge of the CNV signal triggers a single

conversion. At the end of the conversion, the AD4052/AD4058

generate a 16-bit result that the digital host reads via the SPI. Table

16 lists the configuration register settings to select sample mode.

Figure 49 shows a typical connection diagram for the AD4052/

AD4058 digital interface, which includes a recommended 200 Ω

series resistor close to the CNV pin.

Figure 50 shows an interface timing diagram for sample mode.

The tCONV specification quantifies the time delay between the CNV

rising edge and the end of conversion. The digital host must wait

for the maximum tCONV delay before asserting CS and reading the

result over the SPI. The RDY signal acts as an optional hardware

interrupt to synchronize SPI reads to the ADC sampling phases

(see the Data Ready Signal section). To ensure optimal perform-

ance, the digital host must also observe the tQUIET specification that

defines the minimum delay between the final SCLK falling edge and

the next CNV rising edge.

By default, the output data are 16-bits long and are clocked out on

the SDO on each SCLK falling edge. Sample mode also offers an

optional sign-extension byte and CRC byte that can be appended to

the 16-bit ADC data. See the ADC Mode Output Data Format sec-

tion for details on the sample mode SDO data formatting options.

In sample mode, the maximum sampling rate (fS) is limited by the

output data rate of the SPI (fODR), which is a function of the output

data length and serial clock frequency (fSCLK). See the Calculating

Serial Interface Output Data Rate section for details on estimating

the maximum achievable fS for the given operating conditions.

When the DEV_EN signal is enabled, the start of the conversion

is delayed by the programmable tPWR_ON delay relative to the CNV

rising edge. See the Device Enable Signal section and Figure 55 for

specific timing details when using the DEV_EN signal.

Figure 49. Sample Mode Example Connection Diagram

Figure 50. Sample Mode Timing Diagram

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