AD4058BCPZ-R2 datasheet(60/66 Pages) AD

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Data Sheet

AD4052/AD4058

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Rev. B | 60 of 66

Table 41. Bit Descriptions for GP_CONFIG (Continued)

Bits

Bit Name

Description

Reset

Access

0x5: Static Logic Low.

0x6: Static Logic High.

0x7: Invalid.

NOTE - The CHOP signal and the DEV_EN signal cannot be enabled at the same time.

INTERRUPT CONFIGURATION REGISTER

Address: 0x25, Reset: 0x21, Name: INTR_CONFIG

Table 42. Bit Descriptions for INTR_CONFIG

Bits

Bit Name

Description

Reset

Access

[7:6]

RESERVED

Reserved.

0x0

[5:4]

GP1_INTR_EN

GP1 Interrupt Configuration. Selects which of the threshold detection interrupt signals are passed through to the

GP1_INTR output signal.

0x2

R/W

0x0: Neither Interrupt.

0x1: MIN_INTR.

0x2: MAX_INTR.

0x3: Either Interrupt. GP1 outputs the logical OR of MAX_INTR and MIN_INTR signals.

[3:2]

RESERVED

Reserved.

0x0

[1:0]

GP0_INTR_EN

GP0 Interrupt Configuration. Selects which of the threshold detection interrupt signals are passed through to the

GP0_INTR output signal.

0x1

R/W

0x0: Neither Interrupt.

0x1: MIN_INTR. Default.

0x2: MAX_INTR.

0x3: Either Interrupt. GP0 outputs the logical OR of MAX_INTR and MIN_INTR signals.

CHOP SIGNAL CONFIGURATION REGISTER

Address: 0x26, Reset: 0x00, Name: CHOP_CONFIG

Chop Window Length

0xB: 2048.

0xA: 1024.

0x9: 512.

...

0x2: 4.

0x1: 2.

0x0: 1.

[7:4] RESERVED

[3:0] CHOP_WIN_LEN (R/W)

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