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Data Sheet

AD4052/AD4058

THEORY OF OPERATION

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Rev. B | 24 of 66

INTERRUPTS AND CONTROL SIGNALS

The AD4052/AD4058 generate several digital signals for synchro-

nizing the analog front-end and digital back-end processes to the

ADC sampling. These signals can be assigned to the two general

purpose pins (GP0 and GP1) via the GP0_MODE and GP1_MODE

fields in the GP_CONFIG register, respectively. The following sec-

tions describe the functionality and timing details for each of the

AD4052/AD4058 digital signals. Table 13 and Table 41 list the GPx

signal assignments that correspond to each GPx_MODE bit field

setting.

Table 13. GP0 and GP1 Signal Assignment Control

GPx_MODE Setting

GP0 Signal Assignment GP1 Signal Assignment

3'h0

Disabled/high-Z (default) Disabled/high-Z

3'h1

GP0_INTR

GP1_INTR

3'h2

RDY

3'h3

DEV_EN

3'h4

CHOP

3'h5

Logic low

3'h6

Logic high

3'h7

Invalid

DEV_RDY (default)

Static Logic Outputs

The AD4052/AD4058 GP0 and GP1 digital outputs can be set

to a static logic low or logic high level. This function allows the

digital host to control logic settings for external devices through the

AD4052/AD4058 SPI and reduces the required number of GPIO re-

sources. The logic output voltage specifications and corresponding

load current conditions are given by VOL and VOH in Table 1.

Data Ready Signal

The data ready signal (RDY) is an active-low interrupt signal that

indicates when new ADC data are ready to read via the SPI. In

sample mode, RDY goes high at the start of the conversion phase

and returns low at the end of the conversion phase to indicate a

new 16-bit result is available (see Figure 50). In averaging and

burst averaging modes, RDY goes low after NAVG conversions to

indicate a new 20-bit averaged result is available (see Figure 52

and Figure 54).

Threshold Alert Signals

The comparator threshold alert signals MAX_INTR and MIN_INTR

can be routed to the GP0 or GP1 pins via the GP0_INTR and

GP1_INTR signals (see the Autonomous Modes section). Either of

the GPx_INTR signals can be assigned to the MAX_INTR signal,

the MIN_INTR signal, or the logical OR of both, giving the flexibility

to either drive independent hardware interrupts for maximum and

minimum crossings or to combine together for a single interrupt.

By default, MAX_INTR is assigned to GP1_INTR and MIN_INTR is

assigned to GP0_INTR.

The mapping of the alert signals to the GPx pins is controlled via

the GP0_INTR_EN and GP1_INTR_EN bit fields in the INTR_CON-

FIG register (see Table 14 and Table 42).

Table 14. GPx_INTR Settings

GPx_INTR_EN Setting

GPx_INTR Signal Assignment

2'h0

Neither interrupt

2'h1

MIN_INTR

2'h2

MAX_INTR

2'h3

(MAX_INTR) OR (MIN_INTR)

Device Ready Signal

The device ready signal (DEV_RDY) is an active-high signal that

indicates when the AD4052/AD4058 complete power-up or reset

routines and are ready to accept serial interface communications.

The DEV_RDY signal is routed to the GP1 pin after power-up

or reset, so the digital host can monitor it to know when the

AD4052/AD4058 are active. See the Device Reset section for

timing diagrams of the DEV_RDY signal.

Device Enable Signal

The AD4052/AD4058 include a signal chain power-cycling control

signal called DEV_EN. The DEV_EN signal synchronizes the en-

able and power-down states of signal chain devices (such as

amplifiers, sensors, and voltage references) with the ADC sampling

instant, optimizing system power consumption while minimizing

sampling error from power-on delays. Figure 44 shows a typical

application circuit utilizing the DEV_EN signal to power down an

amplifier between samples.

When the DEV_EN signal is enabled, the internal timer acts as a

one-shot timer triggered by the CNV rising edge. The timer delay

(tPWR_ON) controls how long the amplifier is powered on before

the ADC sampling instant and is programmable to tailor to the

connected device's specific power-on settling time specifications.

Table 44 in the Register Details section shows the nominal tPWR_ON

settings available via the TIMER_PWR_ON bit field.

The DEV_EN signal is enabled by assigning it to either the GP0

or GP1 digital outputs (see Table 13 ). The DEV_EN signal can be

configured as active high or active low via the DEV_EN_POL bit

field in the GP_CONFIG register (see Table 41). DEV_EN is active

high by default.

Figure 55, Figure 56, and Figure 57 in the Modes of Operation

section show timing diagrams of the DEV_EN signal and the ADC

sampling instant relative to CNV rising edge. In sample mode

and averaging mode, DEV_EN deasserts after each conversion.

In burst averaging mode, DEV_EN remains asserted until the last

conversion in the burst of samples. DEV_EN is not supported in the

autonomous modes.

Note that the device enable signal (DEV_EN) and the CHOP signal

cannot be enabled at the same time.

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