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Data Sheet

AD4052/AD4058

THEORY OF OPERATION

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Rev. B | 18 of 66

Figure 36. AD4052/AD4058 Functional Block Diagram

OVERVIEW

The AD4052/AD4058 are compact, ultra-low power, 16-bit, Easy

Drive SAR ADCs. The AD4052/AD4058 feature set eases the de-

sign of low-power precision measurement systems by reducing the

AFE design constraints and minimizing the digital host overhead.

The low input capacitance and wide common-mode input range

broaden the selection of compatible AFE components, allowing

for simpler and lower power signal chain solutions. The block

averaging filter provides noise reduction while offloading computa-

tions from the host processor. The internal timer block enables

autonomous monitoring modes, burst sampling, and device power

cycling controls synchronized to the ADC sampling instant. The

CHOP signal can be used as the control signal for an auto-zero

amplifier that employs chopping in applications that require very

low 1/f noise and offset error. Various hardware interrupts allow the

digital host to sleep between user-defined events.

The AD4052/AD4058 offer a unique balance of performance and

power efficiency, with 86.1 dB of SNR and guaranteed INL of ±0.5

LSBs at only 1.35 nJ per conversion. The AD4052 only consumes

2.7 mW at 2 MSPS and the AD4058 only consumes 0.68 mW at

500 kSPS when operated on a single 3.3 V supply. The power

dissipation scales linearly with sample rate for both the AD4052 and

the AD4058 (see Figure 27). The devices consume 4.1 μW standby

power while not performing conversions. A sleep mode is available

to further reduce standby power to 430 nW during long periods of

idle operation.

The AD4052/AD4058 feature 4-wire SPI with CRC for device con-

figuration and ADC data readback, and the SPI is compatible with

1.8 V to 3.3 V logic levels.

The AD4052/AD4058 have several operating modes, each opti-

mized for either high precision measurement or power-efficient

signal monitoring. The Theory of Operation section describes the

AD4052/AD4058 functional blocks, and the Modes of Operation

section describes the utilization of the functional blocks in each

operating mode. The Serial Interface section describes the SPI

protocols for accessing configuration registers and ADC data. The

CONVERTER OPERATION

The AD4052/AD4058 operate in two phases, the acquisition phase

and the conversion phase. In the acquisition phase, the internal

track-and-hold circuitry is connected to each input pin (IN+ and IN−)

and acquires the voltage on each pin independently. The AD4052/

AD4058 remain in the acquisition phase until the convert start

trigger occurs to initiate a conversion. At the start of the conversion

phase, the track-and-hold circuitry samples the acquired analog

input signal, and the SAR ADC core generates a corresponding

16-bit digital code. The conversion phase ends when the 16-bit

conversion result is ready, which is given by the tCONV specification

in Table 2. The AD4052/AD4058 acquisition and conversion phases

overlap to maximize acquisition time (tACQ).

In sample mode and averaging mode, the conversion phase is

started by a rising edge on the CNV pin. The AD4052/AD4058 offer

several modes where the convert start is triggered by an internal

oscillator instead, including the autonomous modes. Refer to the

Modes of Operation section for specific ADC timing information for

each of the relevant operating modes.

Transfer Function

Figure 37 shows the ideal transfer function of the AD4052/AD4058

SAR ADC cores. The AD4052/AD4058 encode the sampled voltage

difference between IN+ and IN− as a fraction of the full-scale range

(FSR) into a 16-bit digital code. The unit of 1 LSB refers to the

smallest discrete voltage step that can be resolved by the ADC and

is a function of the VREF voltage. In averaging and burst averaging

modes, the block averaging filter averages multiple 16-bit samples

into one 20-bit code. Table 11 and Table 12 summarize the mapping

of input voltages to digital output codes.

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