STDRIVE102BH datasheet(17/56 Pages) STMICROELECTRONICS

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Figure 7. VCC thresholds (power-good and UVLO)

VP_GOOD(On)

VCC(On)

VCC

nFAULT

FLAG

Gate drivers active

Gate drivers

LOW

Gate Drivers

VP_GOOD(Off)

VCC(Off)

Gate drivers active

(*)

Note:

(*) The FLAG pin is available only in the STDRIVE102BH.

5.1.2

3.3 V LDO linear regulator

The device integrates a 3.3 V regulator, which supplies the embedded analog front-end (AFE). In addition,

external loads can be connected to the VDD pin, taking care to stay within the operating range. It is

recommended to place a low ESR ceramic capacitor of 4.7 µF 16 V as close as possible to the VDD pin, to

guarantee the stability of the VDD voltage.

The output current of the regulator is limited at IDD,lim, protecting it against short-circuit and overload. The overall

consumption of the external loads plus the AFE must be smaller than this current limitation.

Figure 8. 3.3 V LDO output according to the current load at different REGIN_3V3 input

0,5

1,5

2,5

3,5

Load Current [mA]

REGIN_3V3 > 4 V

REGIN_3V3 = 3.3 V

The regulator is disabled in standby mode in order to reduce the current consumption.

The regulator can be bypassed by connecting the VDD and the REGIN_3V3 pins together and forcing externally a

voltage equal to the target VDD value, and in any case within the operative range of the VDD pin.

The 3.3 V regulator has a dedicated UVLO protection. The UVLO helps to avoid unexpected behavior related to

all the circuitries supplied by the VDD, in particular it avoids spurious events coming from the AFE comparators

and unstable sampling of the TCC and/or IGATE pins.

STDRIVE102BH, STDRIVE102H

Device description

DS14545 - Rev 1

page 17/56

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