ADS7253 datasheet(34/73 Pages) TI2

34 / 73 page

ADS8354, ADS7854, ADS7254

SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014

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8.5.2.1 Configuration Register (CFR)

The device operation configuration is controlled by the configuration register (CFR) status. Data written into the

CFR in a valid frame (F) determine the device configuration for frame (F+1). The bit functions are outlined in

Figure 87. On power-up, all bits in the CFR default to 0.

Figure 87. CFR Bit Functions

RD_CLK_

RD_DATA_

WRITE/READ

ADDR1

ADDR0

INPUT_RANGE

MODE

LINES

REF_SEL

STANDBY

Table 5. Configuration Register (CFR) Field Descriptions

Bit

Field

Type

Reset

Description

WRITE/READ

These bits select the user-programmable register.

R/W

1000 = Select this combination to write to the CFR register and

ADDR1

R/W

to enable bits 11:0

ADDR0

R/W

This bit provides clock mode selection for the serial interface.

0 = Selects 32-CLK mode (default)

RD_CLK_MODE

R/W

1 = Selects 16-CLK mode

(Note that the ADS8354 only supports 32-CLK mode. This bit is

ignored for the ADS8354.)

This bit provides data line selection for the serial interface.

0 = Use SDO_A to output ADC_A data and SDO_B to output of

RD_DATA_LINES

R/W

ADC_B data (default)

1 = Use only SDO_A to output of ADC_A data followed by

ADC_B data

This bit selects the maximum input range for the ADC as a

function of the reference voltage provided to the ADC. See the

INPUT_RANGE

R/W

Analog Inputs section for more details.

0 = FSR equals ±VREF

1 = FSR equals ±2 × VREF

8:7

R/W

This bit must be set to 0 (default)

This bit selects the ADC reference voltage source. Refer to the

Reference section for more details.

REF_SEL

R/W

0 = Use external reference (default)

1 = Use internal reference

This bit is used by the device to enter or exit STANDBY mode.

STANDBY

Refer to the STANDBY Mode section for more details.

R/W

This bit must be set to 0 (default)

3:0

R/W

These bits must be set to 0 (default)

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