ADS7253 datasheet(11/73 Pages) TI2

11 / 73 page

ADS8354, ADS7854, ADS7254

www.ti.com

SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014

7.9 Timing Requirements: Interface Mode

(1)

PARAMETER

ASSOCIATED FIGURES

tCLK

CLOCK period

Figure 1, Figure 90, Figure 91, Figure 92, Figure 93

tACQ

Acquisition time

Figure 90, Figure 91, Figure 92, Figure 93

tCONV

Conversion time

Figure 90, Figure 91, Figure 92, Figure 93

(1)

These parameters are specific to the interface mode of operation. Refer to the Conversion Data Read section for more details.

7.10 Timing Characteristics: Serial Interface

PARAMETER

TEST CONDITIONS

ASSOCIATED FIGURES

MIN

TYP

MAX

UNIT

TIMING REQUIREMENTS

tPH_CK

CLOCK high time

0.4

0.6

tCLK

tPL_CK

CLOCK low time

Figure 1

0.4

0.6

tCLK

fCLK

CLOCK frequency

1 / tCLK

MHz

tPH_CS

CS high time

Figure 1

ADS8354

150

tPH_CS_SHRT

CS high time after frame abort

ADS7854

Figure 98

100

ADS7254

Setup time: CS falling edge to

tSU_CSCK

SCLK falling edge

Delay time: Last SCLK falling edge

tD_CKCS

to CS rising edge

Figure 1

Setup time: DIN data valid to SCLK

tSU_CKDI

falling edge

Hold time: SCLK falling edge to

tHT_CKDI

(previous) data valid on DIN

Power-up time from STANDBY

tPU_STDBY

Figure 95

µs

mode

With internal reference

tPU_SPD

Power-up time from SPD mode

Figure 97

With external reference

TIMING SPECIFICATIONS

ADS8354

32-CLK mode

1.425

µs

Figure 90, Figure 91

32-CLK mode

µs

ADS7854

tTHROUGHPUT

Throughput time

16-CLK mode

Figure 92, Figure 93

µs

32-CLK mode

Figure 90, Figure 91

µs

ADS7254

16-CLK mode

Figure 92, Figure 93

µs

Figure 90, Figure 91,

fTHROUGHPUT

Throughput

1 / tTHROUGHPUT kSPS

Figure 92, Figure 93

Delay time: CS falling edge to data

tDV_CSDO

enable

Delay time: CS rising edge to data

tDZ_CSDO

Figure 1

going to 3-state

Delay time: SCLK falling edge to

tD_CKDO

next data valid

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