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ADS7253 数据表(PDF) 39 Page - Texas Instruments |
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ADS7253 数据表(HTML) 39 Page - Texas Instruments |
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39 / 73 page ![]() 1 2 14 15 16 17 28 29 30 SCLK CS ADS8353, ADS8354 SDO_A Sample N Sample N+1 tACQ tCONV tTHROUGHPUT Data From Sample N 31 32 D1 5-A 18 Data From Sample N B15 B14 B3 SDI 33 34 44 45 46 47 48 ADS7853, ADS7854 SDO_A Data From Sample N ADS7253, ADS7254 SDO_A D1 4-A D4- A D3- A D2- A D1- A D0- A D1 5-B D0- B D1- B D2- B D3- B D4- B D1 3-A D1 2-A D2- A D1- A D0- A 0 0 D1 3-B 0 0 D0- B D1- B D2- B D1 1-A D1 0-A D0- A 0 0 0 0 D1 1-B 0 0 0 0 D0- B B2 B1 B0 X X X X X X X X X X X X X All Devices SDO_B ADS8354, ADS7854, ADS7254 www.ti.com SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014 8.5.3.2.2 32-CLK, Single-SDO Mode (CFR.B11 = 0, CFR.B10 = 1) The 32-CLK, single-SDO mode provides the option of using only one SDO pin (SDO_A) to read conversion results from both ADCs (ADC_A and ADC_B). SDO_B remains in 3-state and can be treated as a no connect (NC) pin. This mode can be selected by writing CFR.B11 = 0 and CFR.B10 = 1. Figure 91 shows a detailed timing diagram for this mode. Figure 91. 32-CLK, Single-SDO Mode Timing Diagram A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A pin. The device converts the sampled analog input during the conversion time (tCONV). SDO_A reads 0 during this period. After competing the conversion process, the sample-and-hold circuit goes back into sample mode. The device outputs the MSB of ADC_A on the SDO_A pin on the 16th SCLK falling edge. The subsequent SCLK falling edges are used to shift out the conversion result of ADC_A followed by the conversion result of ADC_B on the SDO_A pin, as shown in Table 13. Table 13. Data Launch Edge LAUNCH EDGE DEVICE PIN CS SCLK CS ↓ ↓1 — ↓15 ↓16 — ↓27 ↓28 ↓29 ↓30 ↓31 ↓32 — ↓43 ↓44 ↓45 ↓46 ↓47 ↓48 ... ↑ ADS8354 SDO-A 0 0 — 0 D15_A — D4_A D3_A D2_A D1_A D0_A D15_B — D4_B D3_B D2_B D1_B D0_B 0 ... Hi-Z ADS7854 SDO-A 0 0 — 0 D13_A — D2_A D1_A D0_A 0 0 0 — D2_B D1_B D0_B 0 0 0 ... Hi-Z ADS7254 SDO-A 0 0 — 0 D11_A — D0_A 0 0 0 0 0 — D0_B 0 0 0 0 0 ... Hi-Z In this mode, at least 48 SCLK falling edges must be given to validate the read or write frame. A CS rising edge ends the frame and puts the serial bus into 3-state. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: ADS8354 ADS7854 ADS7254 |
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