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ADS7253 数据表(PDF) 41 Page - Texas Instruments

部件名 ADS7253
功能描述  ADSxx54 Dual, High-Speed, 16-, 14-, and 12-Bit, Simultaneous-Sampling, Analog-to-Digital Converters
PDF  73 Pages
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制造商  TI2 [Texas Instruments]
网页  https://www.ti.com
标志 TI2 - Texas Instruments

ADS7253 数据表(HTML) 41 Page - Texas Instruments

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ADS8354, ADS7854, ADS7254
www.ti.com
SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014
A CS falling edge brings the serial data bus out of 3-state and also outputs a 0 on the SDO_A and SDO_B pins.
The subsequent SCLK falling edges are used for conversion and for data transfer using the serial interface, as
shown in Table 15.
The sample-and-hold circuit goes back into sample mode as soon as the conversion process is over.
Table 15. Data Launch Edge
LAUNCH EDGE
DEVICE
PINS
CS
SCLK
CS
↓
↓1
↓2
—
↓13
↓14
↓15
↓16 ...
↑
SDO-A
0
0
D13_A
—
D2_A
D1_A
D0_A
0 ...
Hi-Z
ADS7854
SDO-B
0
0
D13_B
—
D2_B
D1_B
D0_B
0 ...
Hi-Z
SDO-A
0
0
D11_A
—
D0_A
0
0
0 ...
Hi-Z
ADS7254
SDO-B
0
0
D11_B
—
D0_B
0
0
0 ...
Hi-Z
In this mode, at least 16 SCLK falling edges must be given to validate the read or write frame. A CS rising edge
ends the frame and puts the serial bus into 3-state.
Refer to Table 16 for timing specifications specific to this serial interface mode.
Table 16. 16-CLK, Dual-SDO Interface Specific Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING REQUIREMENTS
ADS7854
55.5
ns
tCLK
CLOCK period
ADS7254
55.5
ns
ADS7854
4 × tCLK
ns
tACQ
Acquisition time
ADS7254
6 × tCLK
ns
TIMING SPECIFICATIONS
ADS7854
14 × tCLK
ns
tCONV
Conversion time
ADS7254
12 × tCLK
ns
Copyright © 2013–2014, Texas Instruments Incorporated
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Product Folder Links: ADS8354 ADS7854 ADS7254



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