ADS7253 datasheet(48/73 Pages) TI2

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RFLT ^22

AINP

AINM

GND

ADS8354

ADS7854

ADS7254

RFLT ^22

CFLT _400 pF

FLT

THD

ADC

AMP

ADS8354, ADS7854, ADS7254

SBAS556B – OCTOBER 2013 – REVISED AUGUST 2014

www.ti.com

Application Information (continued)

•

Distortion. Both the ADC and the input driver introduce nonlinearity in a data acquisition block. As a rule of

thumb, to ensure that the distortion performance of the data acquisition system is not limited by the front-end

circuit, the distortion of the input driver should be at least 10 dB lower than the distortion of the ADC, as

shown in Equation 10.

(10)

•

Settling Time. For dc signals with fast transients that are common in a multiplexed application, the input signal

must settle to the desired accuracy at the inputs of the ADC during the acquisition time window. This

condition is critical to maintain the overall linearity performance of the ADC. Typically, the amplifier data

sheets specify the output settling performance only up to 0.1% to 0.001%, which may not be sufficient for the

desired accuracy. Therefore, the settling behavior of the input driver should always be verified by TINA™-

SPICE simulations before selecting the amplifier.

9.1.2 Antialiasing Filter

Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency

content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency

spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the

harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a

low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc

signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow

accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter

bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-

noise ratio (SNR) of the system.

A filter capacitor, CFLT, connected across the ADC inputs (as shown in Figure 99), filters the noise from the front-

end drive circuitry, reduces the sampling charge injection and provides a charge bucket to quickly charge the

internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor

should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input

sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The capacitor

should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and

stable electrical characteristics under varying voltages, frequency, and time.

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier

marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of

the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a

result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,

input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability

and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω

in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can

be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any

resistor mismatch.

Figure 99. Antialiasing Filter

The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI

strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase

margin with the selected filter. If an amplifier has less than a 40° phase margin with 22-

Ω resistors, using a

different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor

is advisable.

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