STA381BWS datasheet(60/174 Pages) STMICROELECTRONICS

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STA381BWS

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DocID018937 Rev 7

6.12

HPCFG register (addr 0x10)

6.13

Configuration register A (addr 0x11)

6.13.1

Master clock select

The STA381BWS supports sampling rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:



32.768 MHz for 32 kHz



45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz



49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin or BICKI pin (depending on the MCS

settings) must be a multiple of the input sampling frequency (fs).

The relationship between the input clock (either XTI or BICKI) and the input sampling rate is

determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine

the PLL factor generating the internal clock and the IR bit determines the oversampling ratio

used internally. In Table 28 MCS 111 and 110 indicate that BICKI has to be used as the

clock source, while XTI is used in all the other cases.

Reserved

MUTE

00000001

Table 26. HPCFG register

Bit

R/W

RST

Name

Description

R/W

MUTE

0: HP/Line out is ON

1: HP/LIne out is muted

FDRB

Reserved

IR1

IR0

MCS2

MCS1

MCS0

01100111

Table 27. Master clock select

Bit

R/W

RST

Name

Description

R/W

MCS0

Selects the ratio between the input I2S sampling

frequency and the input clock.

R/W

MCS1

R/W

MCS2

Obsolete

Product(s)

- Obsolete

Product(s)

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