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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STA381BWS 数据表(PDF) 26 Page - STMicroelectronics |
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STA381BWS 数据表(HTML) 26 Page - STMicroelectronics |
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26 / 174 page  Electrical specifications STA381BWS 26/174 DocID018937 Rev 7 3.6 Power-on/off sequence Figure 4. Power-on sequence Note: The definition of a stable clock is when fmax - fmin < 1 MHz. Section 6.14.1: Serial data interface gives information on setting up the I2S interface. Figure 5. Power-off sequence for pop-free turn-off Note: The register addresses for Soft Mute and Soft EAPD refer to Sound Terminal compatibility (see Section 7: Register description: Sound Terminal compatibility on page 106) and are not the default addresses. Don’t care Don’t care CMD0 CMD1 CMD2 Don’t care Don’t care CMD0 CMD1 CMD2 Don’t care Don’t care Don’t care CMD0 CMD1 CMD2 Don’t care Don’t care CMD0 CMD1 CMD2 Don’t care Don’t care CMD0 CMD1 CMD2 Don’t care Note: no specific VCC and VDD_DIG turn −on sequence is required TR = minimum time between XTI master clock stable and Reset removal: 1 ms TC = minimum time between Reset removal and I2C program, sequence start: 1ms VCC VDD_DIG XTI or BICKI HW RESET I 2C HW PWDN TR TC Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care Note: no specific VCC and VDD_DIG turn −off sequence is required VCC VDD_DIG XTI or BICKI Soft Mute Soft EAPD Reg. 0x07 Data 0xFE Reg. 0x05 Bit 7 = 0 FE Obsolete Product(s) - Obsolete Product(s) |
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