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STA381BWS 数据表(PDF) 71 Page - STMicroelectronics |
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STA381BWS 数据表(HTML) 71 Page - STMicroelectronics |
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71 / 174 page ![]() DocID018937 Rev 7 71/174 STA381BWS Register description: New Map 6.19.2 Channel 3 / line output volume (addr 0x1B) The volume structure of the STA381BWS consists of individual volume registers for each channel and a master volume register that provides an offset to each channel’s volume setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -80 dB. As an example, if CH3VOL = 0x00 or +48 dB and MVOL= -12 dB, then the total gain for channel 3 = +36 dB. The master mute, when set to 1, mutes all channels at once, whereas the individual channel mute (CxM) mutes only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (approximately 96 kHz). A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register, any channel whose total volume is less than -80 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (Section 6.17: Configuration register E (addr 0x15)) on a per-channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately. D7 D6 D5 D4 D3 D2 D1 D0 CH3VOL 01100000 Table 55. Channel 3 volume as a function of CH3VOL[7:0] CH3VOL[7:0] Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB …… 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB …… 11010111 (0xD7) -59.5 dB 11011000 (0xD8) -60 dB 11011001 (0xD9) -61 dB 11011010 (0xDA) -62 dB …… 11101100 (0xEC) -80 dB 11101101 (0xED) Hard channel mute …… 11111111 (0xFF) Hard channel mute Obsolete Product(s) - Obsolete Product(s) |
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