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STA381BWS 数据表(PDF) 64 Page - STMicroelectronics

部件名 STA381BWS
功能描述  Sound Terminal 2.1-channel high-efficiency digital audio system
PDF  174 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA381BWS 数据表(HTML) 64 Page - STMicroelectronics

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STA381BWS
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DocID018937 Rev 7
Table 34. Supported serial audio input formats for LSB-first (SAIFB = 1)
To make the STA381BWS work properly, the serial audio interface LRCKI clock must be
synchronous to the PLL output clock. It means that:
the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on
the settings in Table 30
the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA381BWS will immediately mute the I2S PCM data out (provided to the processing block)
and it will freeze any active processing task.
BICKI
SAI [3:0]
SAIFB
Interface format
32 * fs
1100
1
I2S 15-bit data
1110
1
Left/right-justified 16-bit data
48 * fs
0100
1
I2S 23-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
64 * fs
0000
1
I2S 24-bit data
0100
1
I2S 20-bit data
1000
1
I2S 18-bit data
1100
1
LSB first I2S 16-bit data
0001
1
Left-justified 24-bit data
0101
1
Left-justified 20-bit data
1001
1
Left-justified 18-bit data
1101
1
Left-justified 16-bit data
0010
1
Right-justified 24-bit data
0110
1
Right-justified 20-bit data
1010
1
Right-justified 18-bit data
1110
1
Right-justified 16-bit data
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