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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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STA381BWS 数据表(PDF) 90 Page - STMicroelectronics |
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STA381BWS 数据表(HTML) 90 Page - STMicroelectronics |
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90 / 174 page  Register description: New Map STA381BWS 90/174 DocID018937 Rev 7 6.27 PLL configuration registers (address 0x52; 0x53; 0x54; 0x55; 0x56; 0x57) By default, the STA381BWS is able to configure the embedded PLL automatically depending on the MCS bits (reg 0x00). For certain applications and to provide flexibility to the user, a manual PLL configuration can be used (setting PLL_DIRP to ‘1’) The output PLL frequency formula is: where Fin is the input clock frequency from the pad. D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[15:8] 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC[7:0] 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DITH[1:0] PLL_NDIV[5:0] 00000000 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DPD PLL_FCT PLL_STB PLL_STBBYP PLL_IDIV[3:0] 00000000 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved PLL_DIRP PLL_PWD PLL_BYP OSC_PD Reserved BOOST32K 00000000 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved BYPSTATE PDSTATE OSCOK LOWCK NA NA NA NA NA NA NA NA Table 80. PLL factors PLL parameter Min Max FRAC 0 65535 IDIV 0 3 NDIV 5 55 Fin NDIV IDIV 1 + --------------------------- FRAC 65536 ----------------- + Obsolete Product(s) - Obsolete Product(s) |
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