STA381BWS datasheet(88/174 Pages) STMICROELECTRONICS

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STA381BWS

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DocID018937 Rev 7

6.25

Fault-detect recovery constant registers (addr 0x3C - 0x3D)

The FDRC bits specify the 16-bit fault-detect recovery time delay. When FAULT is asserted,

the TRISTATE output is immediately asserted low and held low for the time period specified

by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x300C gives approximately 1 sec.

0x0000 is a reserved value.

6.26

Extended configuration register (addr 0x47)

The extended configuration register provides access to biquad 5, 6 and 7.

6.26.1

Extended post-scale range

Table 74. Extended post-scale range

Post-scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied

to the coefficient RAM value, so post-scale can act as a gain too.

6.26.2

Extended attack rate

The attack rate shown in Table 67 can be extended to provide up to an 8 dB/ms attack rate

on both limiters.

Table 75. Extended attack rate, limiter 1

FDRC15

FDRC14

FDRC13

FDRC12

FDRC11

FDRC10

FDRC9

FDRC8

00110000

FDRC7

FDRC6

FDRC5

FDRC4

FDRC3

FDRC2

FDRC1

FDRC0

00001100

Reserved

PS48DB

XAR1

XAR2

BQ5

BQ6

BQ7

000111

PS48DB

Mode

Post-scale value is applied as defined in the coefficient RAM

Post-scale value is applied with a +48 dB offset with respect to the

coefficient RAM value

XAR1

Mode

Limiter1 attack rate is configured using Table 67

Limiter1 attack rate is 8 dB/ms

Obsolete

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