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STA381BWS 数据表(PDF) 115 Page - STMicroelectronics |
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STA381BWS 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 174 page  DocID018937 Rev 7 115/174 STA381BWS Register description: Sound Terminal compatibility 7.3 Configuration register C (addr 0x02) 7.3.1 FFX compensating pulse size register Table 6: 7.4 Configuration register D (addr 0x03) 7.4.1 DSP bypass Setting the DSPB bit bypasses the EQ function of the STA381BWS. D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved CSZ3 CSZ2 CSZ1 CSZ0 Reserved Reserved 10010111 Table 112. FFX compensating pulse size bits Bit R/W RST Name Description 2 R/W 1 CSZ0 When OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods. 3 R/W 1 CSZ1 4 R/W 1 CSZ2 5 R/W 0 CSZ3 Table 113. Compensating pulse size CSZ[3:0] Compensating pulse size 0000 0 ns (0 ticks) compensating pulse size 0001 20 ns (1 tick) clock period compensating pulse size …… 1111 300 ns (15 ticks) clock period compensating pulse size D7 D6 D5 D4 D3 D2 D1 D0 SME ZDE Reserved BQL PSL DSPB Reserved Reserved 00011000 Table 114. DSP bypass Bit R/W RST Name Description 2 R/W 0 DSPB 0: Normal operation 1: Bypass of biquad and bass/treble functions Obsolete Product(s) - Obsolete Product(s) |
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