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STA381BWS 数据表(PDF) 166 Page - STMicroelectronics |
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STA381BWS 数据表(HTML) 166 Page - STMicroelectronics |
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166 / 174 page  Register description: Sound Terminal compatibility STA381BWS 166/174 DocID018937 Rev 7 7.30 MISC3 (address 0x6E) After SRESET is written, the last IC acknowledge is skipped and the EAPD bit (reg 0x16 bit D7) is set to1 instead of the 0 default value obtained after the hardware reset. 7.31 MISC4 (address 0x7E) D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved reserved SRESET reserved reserved 00000000 Table 181. Misc register 3 Bit R/W RST Name Description 2 R/W 0 SRESET 0: normal operation 1: reset the device D7 D6 D5 D4 D3 D2 D1 D0 SMAP reserved reserved reserved reserved reserved reserved reserved 10000000 Table 182. MISC4 Bit R/W RST Name Description 7 1 SMAP 1: NEWMAP 0: STMAP Obsolete Product(s) - Obsolete Product(s) |
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