STA339BWS datasheet(44/79 Pages) STMICROELECTRONICS

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STA339BWS

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DocID015276 Rev 9

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This

7.2

Volume control registers (addr 0x06 - 0x0A)

The volume structure of the STA339BWS consists of individual volume registers for each

channel and a master volume register that provides an offset to each channels volume

setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB

to -80 dB.

As an example if C3VOL = 0x00 or +48 dB and MVOL = 0x18 or -12 dB, then the total gain

for channel 3 = +36 dB.

The channel mutes provide a “soft mute” with the volume ramping down to mute in

4096 samples from the maximum volume setting at the internal processing rate

(approximately 96 kHz).

All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E

(addr 0x04)) on a per channel basis as this creates the smoothest possible volume

transitions. When ZCE = 0, volume updates occur immediately.

Table 50. External amplifier power down

Bit

R/W

RST

Name

Description

7R/W

EAPD

0: external power stage power down active

1: normal operation

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