STA339BWS datasheet(20/79 Pages) STMICROELECTRONICS

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I2C bus specification

STA339BWS

20/79

DocID015276 Rev 9

I2C bus specification

The STA339BWS supports the I2C protocol via the input ports SCL and SDA_IN (master to

slave) and the output port SDA_OUT (slave to master). This protocol defines any device

that sends data on to the bus as a transmitter and any device that reads the data as a

receiver. The device that controls the data transfer is known as the master and the other as

the slave. The master always starts the transfer and provides the serial clock for

synchronization. The STA339BWS is always a slave device in all of its communications. It

supports up to 400 kb/s (fast-mode bit rate).

For correct operation of the I2C interface ensure that the master clock generated by the PLL

has a frequency at least 10 times higher than the frequency of the applied SCL clock.

6.1

Communication protocol

6.1.1

Data transition or change

Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition

while the clock is high is used to identify a START or STOP condition.

6.1.2

Start condition

START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is

stable in the high state. A START condition must precede any command for data transfer.

6.1.3

Stop condition

STOP is identified by low to high transition of SDA while SCL is stable in the high state. A

STOP condition terminates communication between STA339BWS and the bus master.

6.1.4

Data input

During the data input the STA339BWS samples the SDA signal on the rising edge of SCL.

For correct device operation the SDA signal must be stable during the rising edge of the

clock and the data can change only when the SCL line is low.

6.2

Device addressing

To start communication between the master and the STA339BWS, the master must initiate

with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)

corresponding to the device select address and read or write mode bit.

The seven most significant bits are the device address identifiers, corresponding to the I2C

bus definition. In the STA339BWS the I2C interface has two device addresses depending on

the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to

0 for write. After a START condition the STA339BWS identifies the device address on the

SDA bus and if a match is found, acknowledges the identification during the 9th bit time

frame. The byte following the device identification is the address of a device register.

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