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STA339BWS 数据表(PDF) 16 Page - STMicroelectronics

部件名 STA339BWS
功能描述  2.1-channel 40-watt high-efficiency digital system Sound Terminal
PDF  79 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA339BWS 数据表(HTML) 16 Page - STMicroelectronics

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Electrical specifications
STA339BWS
16/79
DocID015276 Rev 9
3.6
Power on/off sequence
Figure 4. Power-on sequence
Note:
The definition of a stable clock is when fmax - fmin < 1 MHz.
Section Serial audio input interface format on page 27 gives information on setting up the
I2S interface.
Figure 5. Power-off sequence for pop-free turn-off
Don’t care
Don’t care
CMD0
CMD1
CMD2
VCC
VDD_Dig
XTI
Reset
I2C
PWDN
TR
TC
Don’t care
Don’t care
CMD0
CMD1
CMD2
VCC
VDD_Dig
XTI
Reset
I2C
PWDN
TR
TC
Don’t care
Don’t care
Don’t care
CMD0
CMD1
CMD2
VCC
VDD_Dig
XTI
Reset
I2C
PWDN
TR
TC
Don’t care
Don’t care
CMD0
CMD1
CMD2
VCC
VDD_Dig
XTI
Reset
I2C
PWDN
TR
TC
Don’t care
Don’t care
CMD0
CMD1
CMD2
VCC
VDD_Dig
XTI
Reset
I2C
PWDN
TR
TC
Don’t care
Note: no specific VCC and
VDD_DIG turn
on sequence
is required
TR = minimum time between XTI master clock stable and Reset removal: 1 ms
TC = minimum time between Reset removal and I2C program, sequence start: 1ms
Don’t care
VCC
VDD_Dig
XTI
Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care
Don’t care
Don’t care
VCC
VDD_Dig
XTI
Don’t care
Soft Mute
Reg. 0x07
Data 0xFE
Soft EAPD
Reg. 0x05
Bit 7 = 0
Don’t care
FE
Don’t care
Don’t care
Note: no specific VCC and
VDD_DIG turn
off sequence
is required



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