STA339BWS datasheet(47/79 Pages) STMICROELECTRONICS

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STA339BWS

7.3

Audio preset registers (addr 0x0B and 0x0C)

7.3.1

Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 66.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Table 54.

7.3.2

Audio preset register 2 (addr 0x0C)

AM interference frequency switching

Reserved

AMGC[1]

AMGC[0]

Reserved

Table 54. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0]

Mode

User programmable GC

AC no clipping 2.1

AC limited clipping (10%) 2.1

DRC night-time listening mode 2.1

XO3

XO2

XO1

XO0

AMAM2

AMAM1

AMAM0

AMAME

Table 55. AM interference frequency switching bits

Bit

R/W

RST

Name

Description

R/W

AMAME

Audio preset AM enable

0: switching frequency determined by PWMS setting

1: switching frequency determined by AMAM settings

Table 56. Audio preset AM switching frequency selection

AMAM[2:0]

48 kHz/96 kHz input fs

44.1 kHz/88.2 kHz input fs

000

0.535 MHz - 0.720 MHz

0.535 MHz - 0.670 MHz

001

0.721 MHz - 0.900 MHz

0.671 MHz - 0.800 MHz

010

0.901 MHz - 1.100 MHz

0.801 MHz - 1.000 MHz

011

1.101 MHz - 1.300 MHz

1.001 MHz - 1.180 MHz

100

1.301 MHz - 1.480 MHz

1.181 MHz - 1.340 MHz

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