L9300 datasheet(99/178 Pages) STMICROELECTRONICS

99 / 178 page

Table 56. SPI register addresses

Page ID [binary]

Macro Function

Address Space Name

SPI Base Address

[hex]

[binary]

000

Solenoid Channel 1

Channel_1_BaseAddress

0x00

000 0000

001

Solenoid Channel 2

Channel_2_BaseAddress

0x10

001 0000

010

Solenoid Channel 3

Channel_3_BaseAddress

0x20

010 0000

011

Solenoid Channel 4

Channel_4_BaseAddress

0x30

011 0000

100

Solenoid Channel 5

Channel_5_BaseAddress

0x40

100 0000

101

Solenoid Channel 6

Channel_6_BaseAddress

0x50

101 0000

11x

Global

GLOBAL_BaseAddress

0x60

11x 0000

Note:

Assumptions on solenoid channel status.

Solenoid Channel State: (DISABLED, TRISTATED, ACTIVE);

DISABLED: Channel inactive, Driver Hi impedance, no diagnosis available.

TRISTATED: Channel enabled, Driver Hi impedance, Thermal/OFF diagnosis available.

ACTIVE: Channel enabled, Driver operating according PWM, Thermal/ON diagnosis available.

During power on sequence, all solenoid channels are in DISABLED state. At the end of power on sequence,

channel status is controlled by EN_DR pin status (0 => DISABLED) and SPI registers (SERVENA and

SOLENDRV).

In the following tables RES1 reset event has to be intended as the combination of internal events triggering reset

pin low and RES1 trigger from external command; unused bits for SDO data fields are reported as 0 in the data

out frame.

Table 57. Register summary table

Service enable

SERVENA

Service Fault

SERVFLT

Service Fault Mask

SERVFLTMSK

Temperature sensor

TEMPSENS

WSI Registers

WSITEST

WSI CONFIGURATION CH_1_2

WSIRSCR0

WSI CONFIGURATION CH_3_4

WSIRSCR3

WSI CONTROL

WSICTRL

WSI AUXILIARY CONFIGURATION

WSIAUXCONF

WSI REMOTE SENSOR DATA/FAULT REGISTER 0 to 3

WSIRSDR[0:3]

WSI REMOTE SENSOR DATA REGISTER 4 to 7

WSIRSDR[4:7]

WSI REMOTE SENSOR DATA REGISTER 8 to 11

WSIRSDR[8:11]

TRK-CAN DISABLE

TRKDISABLE

TRK-CAN FAULT

TRKFAULT

Pump Configuration

PUMPCFG

Q&A Seed/Answer

WDG2SEEDANS

Q&A Status

WDG2STATUS

Q&A Answer Timing

WDG2ANSTMG

Q&A Request Timing

WDG2RQTMG

L9300

SPI interface and register mapping

DS12258 - Rev 5

page 99/178

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