L9300 datasheet(35/178 Pages) STMICROELECTRONICS

35 / 178 page

High-speed operation

The number of datalog bit is reduced at high-speed operations (see next figure). There are four dedicated bits on

the SPI WSIRSDRx register which show how many valid bits are coming from the VDA sensor.

Figure 20. Signal monitoring: high Speed

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5

tp/2

Initial bit

Speed pulse

Sensor output

Current

Data log

Speed pulse

t_mc

_if

GADG1407170839PS

Standstill operation

The ASIC is able to understand whether the VDA sensor is in standstill mode. Standstill operation frames are

composed as shown in the next figure. In this case the speed pulse is not modulated at current level I_high but a

level I_mid is used.

The expected number of transmitted datalog bit is equal to 9 but no automatic check is performed.

Figure 21. Signal monitoring: standstill

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Parity

tp/2

Initial bit

Speed pulse

Sensor output

Current

Data log

Speed pulse

t_stop

GADG1407170854PS

Start & stop condition for data decoding

According to the sensor status, the starting and the end point for decoding the VDA data can slightly vary. The

different behaviors are summarized by the table below.

L9300

Power supply

DS12258 - Rev 5

page 35/178

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