 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
L9300 数据表(PDF) 21 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L9300 数据表(HTML) 21 Page - STMicroelectronics |
|
|
21 / 178 page  Symbol Parameter Test condition Min Typ Max Unit Pin VDD1_ovs_1 a Overshoot VBATP step on Vout1 VBATP step from 5.5 V to 13 V during 10 µS, considering 1 µH wiring harness, Guaranteed by design 5.5 V VDD1 VDD1_ovs_2 a Overshoot VBATP step on Vout2 VBATP step from 5.5 V to 13 V during 10 µS, considering 1 µH wiring harness, Guaranteed by design 7.5 V VDD1 PSRR PSRR VBATP = 13 V, IVDD1 = 1.3 A, Vnoise = 1 Vpp, fnoise = 100-200 Hz, CVDD1 = 22 µF, LVROUT = 22 µH Guaranteed by design 50 dB VDD1 VROUT_ovc Ipeak limitation Open loop, current ramp on VROUT 2.5 3.5 A VROUT VROUT_min_duty VDD1 output stage minimum on time duration Design info, Guaranteed by design 100 300 ns VROUT Sw_fr Switching frequency fOSCINT/34 kHz VROUT Buck_Rds_ON High–side Rds_ON Tj=150 °C 0.35 Ω VROUT Buck_Rds_ON High–side Rds_ON Tj=175 °C, Guaranteed by design 0.4 Ω VROUT Buck_ton High–side ton Guaranteed by design 5 40 ns VROUT Buck_toff High–side toff Guaranteed by design 5 40 ns VROUT VDD1 Diagnostic T_SD_VDD1 Temperature shut down 175 185 °C VROUT T_SD_hy Temperature shut down hysteresis 5 10 °C VROUT T_SD_deglitch Digital deglitch filter time Guaranteed by scan 7.5 10 12.5 µs VROUT 8.1.3 VDD1 error handling Table 7. VDD1 type of errors Type of error Detection condition Action Clear SPI flag Restart condition VDD1 overcurrent ON state VDD1 OVER CURRENT SPI fault bit (4) latched in SERVFLT register On read N.A. VDD1 overtemperature ON state If current limitation is not triggered: no action If current limitation is triggered: all outputs except Charge Pump, CAN and GPO disabled, all regulators disabled, power up sequence interrupted and T_SD_VDD1 SPI fault bit (5) latched in SERVFLT register On read Automatic restart with re-trigger of power-up sequence after OT fault disappears. 8.2 VDD2 8.2.1 VDD2 functional description VDD2 is an internal regulator that is configurable through VDD2_SEL pin. If 3.3 V ≤ VDD2_SEL ≤ 5 V, the regulator tracks VDD2_SEL while if VDD2_SEL = 0 V VDD2 works as linear 5 V regulator. VDD_SUP is the supply voltage of VDD2 regulator that can be connected externally to VBATP or, to limit the power dissipation, to VDD1. Since VDD2 could be used to track either VDD3 or VDD4 voltages, VDD2 enable and configuration pin is sensed and latched at power up only after VDD3 and VDD4 voltages are above their own undervoltage thresholds: this is intended to avoid wrong configuration latch during the VDD3 and VDD4 rising phase. Echo of the latched VDD2 configuration is available in the SPI registers. L9300 Power supply DS12258 - Rev 5 page 21/178 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
