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L9300 数据表(PDF) 13 Page - STMicroelectronics |
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L9300 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 178 page  If the device receives an SPI command to refresh the keep-alive bit within the first keep-alive period the device remains awake. Once the keep-alive bit is refreshed a new KA_period starts and so forth. To stay on the keep- alive bit should be refreshed at each KA_period. 7.4 Power down The power down, depending on the keep on condition that is maintaining on the device, can happen in three different ways. In Figure 6 the power down related to a high low transition on the WAKE pin. In Figure 7 the power down related to the removal of power hold bit. In Figure 8 the power down related to the not refreshing keep-alive bit from the microcontroller. During power down all the regulators are switched off at the same time except VDD4 that is delayed by a fixed timing, provided that ASIC battery is kept supplied. No voltage control is performed during power down; in case the relative voltage between regulators is needed it has to be guaranteed through external components. L9300 Power up and power down DS12258 - Rev 5 page 13/178 |
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