TUSB8043AI datasheet(21/62 Pages) TI2

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TUSB8043A

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SLLSF94 – JUNE 2019

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8.3.6 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series

resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used.

The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and

Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the

load capacitance value.

8.3.7 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or

better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak

jitter after applying the USB 3.2 Gen1 jitter transfer function. XI should be tied to the 1.8-V clock source and XO

should be left floating.

8.3.8 Power-Up and Reset

The TUSB8043A does not have specific power sequencing requirements with respect to the core power (VDD)

or I/O and analog power (VDD33) as long as GRSTz is held in an asserted state while supplies ramp. The core

power (VDD) or I/O power (VDD33) may be powered up for an indefinite period of time while the other is not

powered up if all of these constraints are met:

•

All maximum ratings and recommended operating conditions are observed.

•

All warnings about exposure to maximum rated and recommended conditions are observed, particularly

junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the

device.

•

Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down

when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in the

recommended operating range to the de-assertion of GRSTz. This can be generated using programmable-delay

supervisory device or using an RC circuit. When a RC circuit is used, the external capacitor size chosen must be

large enough to meet the 3ms minimum duration requirement. The R of the RC circuit is the internal RPU.

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