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TUSB8043AI 数据表(PDF) 12 Page - Texas Instruments |
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TUSB8043AI 数据表(HTML) 12 Page - Texas Instruments |
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12 / 62 page ![]() 12 TUSB8043A SLLSF94 – JUNE 2019 www.ti.com Product Folder Links: TUSB8043A Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) over operating free-air temperature and voltage range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (2) Applies to external outputs and bi-directional buffers (3) Applies to GRSTZ (4) Applies to pins with internal pullups/pulldowns. (5) Applies to external input buffers VIL Low-level input voltage(1) 0 0.8 V VI Input voltage 0 3.6 V VO Output voltage(2) 0 3.6 V tt Input transition time (tRISE and tFALL) 25 ns VHYS Input hysteresis(3) 1.3 x VDD33 V VOH High-level output voltage IOH = -4 mA 2.4 V VOL Low-level output voltage IOH = 4 mA 0.4 V IOZP High-impedance output current with internal pullup or pulldown resistor.(4) VI = 0 to VDD33; -250 250 µA II Input current(5) VI = 0 to VDD33; -15 15 µA RPD Internal pull-down resistance 13.5 19 27.5 kΩ RPU Internal pull-up resistance 14.5 19 25 kΩ (1) As long as GRSTz is de-asserted after both supplies are stable, there is no power-on relationship between VDD33 and VDD. If GRSTz is only connected to a capacitor to GND, then VDD must be stable minimum of 10 µs before VDD33. (2) An active reset is required if the VDD33 supply is stable before VDD supply. This active reset shall meet the 3 ms power-up delay counting from both power supplies stable to de-assertion of GRSTz. (3) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL. 7.6 Timing Requirements MIN NOM MAX UNIT Power-on timings. Refer to Figure 1 td1 VDD stable before VDD33 stable. (1) (2) 0 ms td2 VDD and VDD33 before de-assertion of GRSTz. 3 ms tsu_io Setup for MISC inputs. (3) 0.1 µs thd_io Hold for MISC inputs. (3) 0.1 µs tVDD33_RAM P VDD33 supply ramp requirement. 0.2 100 ms tVDD_RAMP VDD supply ramp requirement. 0.2 100 ms |
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