TUSB8043AI datasheet(28/62 Pages) TI2

28 / 62 page

TUSB8043A

SLLSF94 – JUNE 2019

www.ti.com

Product Folder Links: TUSB8043A

Submit Documentation Feedback

8.5.7 Device Configuration Register

Figure 8. Register Offset 5h

Bit No.

Reset State

Table 12. Bit Descriptions – Device Configuration Register

Bit

Field

Type

Description

customStrings

Custom strings enable. This bit controls the ability to write to the

Manufacturer String Length, Manufacturer String, Product String

Length, Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers are read only

1 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers may be

loaded by EEPROM or written by SMBus

The default value of this bit is 0.

customSernum

Custom serial number enable. This bit controls the ability to write to the

serial number registers.

0 = The Serial Number String Length and Serial Number String

registers are read only

1 = Serial Number String Length and Serial Number String registers

may be loaded by EEPROM or written by SMBus

The default value of this bit is 0.

u1u2Disable

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled

1 = U1/U2 support is disabled, the TUSB8043A will not initiate or

accept any U1 or U2 requests on any port, upstream or downstream,

unless it receives or sends a Force_LinkPM_Accept LMP. After

receiving or sending an FLPMA LMP, it continues to enable U1 and U2

according to USB 3.2 protocol until it gets a power-on reset or is

disconnected on its upstream port.

When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit

from the contents of the EEPROM.

When the TUSB8043A is in SMBUS mode, the value may be over-

written by an SMBus host.

RSVD

Reserved. This bit is reserved and returns 1 when read.

ganged

Ganged. This bit is loaded at the de-assertion of reset with the value of

the GANGED/SMBA2/HS_UP pin.

0 = When fullPwrMgmtz = 0, each port is individually power switched

and enabled by the PWRCTL[4:1]/BATEN[4:1] pins

1 = When fullPwrMgmtz = 0, the power switch control for all ports is

ganged and enabled by the PWRCTL[4:1]/BATEN1 pin

When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit

from the contents of the EEPROM.

When the TUSB8043A is in SMBUS mode, the value may be over-

written by an SMBus host.

fullPwrMgmtz

Full Power Management. This bit is loaded at the de-assertion of reset

with the value of the FULLPWRMGMTz/SMBA1/SS_UP pin.

0 = Port power switching status reporting is enabled

1 = Port power switching status reporting is disabled

When the TUSB8043A is in I2C mode, the TUSB8043A loads this bit

from the contents of the EEPROM.

When the TUSB8043A is in SMBUS mode, the value may be over-

written by an SMBus host.

u1u2TimerOvr

U1 U2 Timer Override. When this field is set, the TUSB8043A

overrides the downstream ports U1/U2 timeout values set by USB 3.2

Host software. If software sets value in the range of 1h - FFh, the

TUSB8043A uses the value of FFh. If software sets value to 0, then

TUSB8043A uses value of 0. REG_09h [6] must be set to enable this

feature.

RSVD

Reserved. This field is reserved and returns 0 when read.

TUSB8043AI 数据表(PDF) 28 Page - Texas Instruments

TUSB8043AI 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载

链接网址

TUSB8043AI 数据表(PDF) 28 Page - Texas Instruments

TUSB8043AI 数据表(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表 下载

链接网址

数据表下载