TUSB8043AI datasheet(7/62 Pages) TI2

7 / 62 page

TUSB8043A

www.ti.com

SLLSF94 – JUNE 2019

Product Folder Links: TUSB8043A

Submit Documentation Feedback

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

SCL/SMBCLK

I/O, PD

I2C clock/SMBus clock. Function of pin depends on the setting of the SMBUSz input.

When SMBUSz = 1, this pin acts as the serial clock interface for an I2C EEPROM.

When SMBUSz = 0, this pin acts as the serial clock interface for an SMBus host.

Can be left unconnected if external interface not implemented.

SDA/SMBDAT

I/O, PD

I2C data/SMBus data. Function of pin depends on the setting of the SMBUSz input.

When SMBUSz = 1, this pin acts as the serial data interface for an I2C EEPROM.

When SMBUSz = 0, this pin acts as the serial data interface for an SMBus host.

Can be left unconnected if external interface not implemented.

SMBUSz/SS_SUSPEND

I/O, PU

I2C/SMBus mode select/SuperSpeed USB Suspend Status. The value of the pin is sampled

at the de-assertion of reset set I2C or SMBus mode as follows:

1 = I2C Mode Selected

0 = SMBus Mode Selected

Can be left unconnected if external interface not implemented.

After reset, this signal indicates the SuperSpeed USB Suspend status of the upstream port if

enabled through the stsOutputEn bit in the Additional Feature Configuration register. When

enabled, a value of 1 indicates the connection is suspended.

Test and Miscellaneous Signals

FULLPWRMGMTz/FULL

AUTOz/SMBA1/SS_UP

I/O, PD

Full power management enable/SMBus address bit 1/SuperSpeed USB Connection Status

Upstream port.

The value of the pin is sampled at the de-assertion of reset to set the power switch control

follows:

0 = Power switching and over current inputs supported

1 = Power switching and over current inputs not supported

Full power management is the ability to control power to the downstream ports of the

TUSB8043A using PWRCTL[4:1]/BATEN[4:1].

If BATENx = 1 on any port, full power management must be enabled so the value of the

terminal is sampled at the de-assertion to initialize the value of the FULLAUTOz bit.

When AUTOENz = 0 and FULLAUTOz = 0: all ACP modes are supported.

When AUTOENz = 0 and FULLAUTOz = 1:only highest current ACP mode is used in auto

mode.

When SMBus mode is enabled, this pin sets the value of the SMBus slave address bit 1.

Can be left unconnected if full power management and SMBus are not implemented.

After reset, this signal indicates the SuperSpeed USB connection status of the upstream port

if enabled through the stsOutputEn bit in the Additional Feature Configuration register. When

enabled a value of 1 indicates the upstream port is connected to a SuperSpeed USB capable

port.

Note: Power switching must be supported for battery charging applications.

PWRCTL_POL

I/O, PU

Power Control Polarity.

The value of the pin is sampled at the de-assertion of reset to set the polarity of

PWRCTL[4:1].

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high

TUSB8043AI 数据表(PDF) 7 Page - Texas Instruments

TUSB8043AI 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载

链接网址

TUSB8043AI 数据表(PDF) 7 Page - Texas Instruments

TUSB8043AI 数据表(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表 下载

链接网址

数据表下载