STM32F427AI datasheet(167/240 Pages) STMICROELECTRONICS

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DS9405 Rev 12

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STM32F427xx STM32F429xx

Electrical characteristics

197

IDDA(4)

DAC DC VDDA

current consumption in

quiescent mode(3)

280

380

µA

With no load, middle code

(0x800) on the inputs

475

625

µA

With no load, worst code

(0xF1C) at VREF+ = 3.6 V in

terms of DC consumption on

the inputs

DNL(4)

Differential non

linearity Difference

between two

consecutive code-

1LSB)

±0.5 LSB

Given for the DAC in 10-bit

configuration.

±2

LSB

Given for the DAC in 12-bit

configuration.

INL(4)

Integral non linearity

(difference between

measured value at

Code i and the value

at Code i on a line

drawn between Code

0 and last Code 1023)

±1

LSB

Given for the DAC in 10-bit

configuration.

±4

LSB

Given for the DAC in 12-bit

configuration.

Offset(4)

Offset error

(difference between

measured value at

Code (0x800) and the

ideal value = VREF+/2)

±10

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12 LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

Gain

error(4)

Gain error

±0.5

Given for the DAC in 12-bit

configuration

tSETTLIN

(4)

Settling time (full

scale: for a 10-bit input

code transition

between the lowest

and the highest input

codes when

DAC_OUT reaches

final value ±4LSB

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

THD(4)

Total Harmonic

Distortion

Buffer ON

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Update

rate(2)

Max frequency for a

correct DAC_OUT

change when small

variation in the input

code (from code i to

i+1LSB)

MS/

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

Table 86. DAC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ Max Unit

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