STM32F427AI datasheet(237/240 Pages) STMICROELECTRONICS

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DS9405 Rev 12

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STM32F427xx STM32F429xx

Revision history

239

17-Sep-2015

Updated notes related to the minimum and maximum values

guaranteed by design, characterization or test in production.

Updated IDD_STOP_UDM in Table 27: Typical and maximum current

consumptions in Stop mode.

Removed note related to tests in production in Table 24: Typical and

maximum current consumption in Run mode, code with data

processing running from Flash memory (ART accelerator enabled

except prefetch) or RAM and Table 26: Typical and maximum current

consumption in Sleep mode.

Updated Table 41: HSI oscillator characteristics. Figure 31 renamed

ACCHSI accuracy versus temperature and updated.

Updated Figure 38: SPI timing diagram - slave mode and CPHA = 0.

Updated Section : Ethernet characteristics.

Updated Table 43: Main PLL characteristics, Table 44: PLLI2S (audio

PLL) characteristics and Table 45: PLLISAI (audio and LCD-TFT PLL)

characteristics.

Removed note 1 in Table 75: ADC static accuracy at fADC = 18 MHz,

Table 76: ADC static accuracy at fADC = 30 MHz and Table 77: ADC

static accuracy at fADC = 36 MHz.

Updated td(SDCLKL _Data) and th(SDCLKL _Data) in Table 104:

SDRAM write timings.

Added Figure 96: UFBGA169 - 169-ball, 7 x 7 mm, 0.50 mm pitch, ultra

fine pitch ball grid array recommended footprint and Table 117:

UFBGA169 recommended PCB design rules (0.5 mm pitch BGA).

Added Figure 99: UFBGA176+25-ball, 10 x 10 mm, 0.65 mm pitch,

ultra fine pitch ball grid array package recommended footprint and

Table 119: UFBGA176+25 recommended PCB design rules (0.65 mm

pitch BGA).

30-Nov-2015

Updated |VSSX -VSS| in Table 14: Voltage characteristics to add

VREF-.

Updated td(TXEN) and td(TXD) minimum value in Table 72: Dynamics

characteristics: Ethernet MAC signals for RMII and Table 73: Dynamics

characteristics: Ethernet MAC signals for MII.

Added VREF- in Table 74: ADC characteristics.

Added A1 minimum and maximum values in Table 111: WLCSP143 -

143-ball, 4.521x 5.547 mm, 0.4 mm pitch wafer level chip scale

package mechanical data. Updated Figure 86: LQFP144-144-pin, 20 x

20 mm low-profile quad flat package outline.

Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch

ultra thin fine pitch ball grid array package outline and Table 118:

UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball

grid array package mechanical data. Updated Figure 101: TFBGA216 -

216 ball 13 × 13 mm 0.8 mm pitch thin fine pitch ball grid array package

outline and Table 120: TFBGA216 - 216 ball 13 × 13 mm 0.8 mm pitch

thin fine pitch ball grid array package mechanical data.

21-Jan-2016

Updated Figure 22: Power supply scheme.

Added td(TXD) values corresponding to 1.71 V < VDD < 3.6 V in Table

72: Dynamics characteristics: Ethernet MAC signals for RMII.

Table 125. Document revision history

Date

Revision

Changes

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