STM32F427AI datasheet(238/240 Pages) STMICROELECTRONICS

238 / 240 page

Revision history

STM32F427xx STM32F429xx

238/240

DS9405 Rev 12

18-Jul-2016

Updated Figure 1: Compatible board design

STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package.

Added mission profile compliance with JEDEC JESD47 in Section 6.2:

Absolute maximum ratings.

Changed Figure 31 HSI deviation versus temperature to ACCHSI

versus temperature.

Updated RLOAD in Table 85: DAC characteristics.

Added note 2. related to the position of the 0.1 µF capacitor below

Figure 37: Recommended NRST pin protection.

Updated Figure 40: SPI timing diagram - master mode.

Added reference to optional marking or inset/upset marks in all

package device marking sections. Updated Figure 85: WLCSP143

marking example (package top view), Figure 88: LQFP144 marking

example (package top view), Figure 91: LQFP176 marking (package

top view), Figure 94: LQFP208 marking example (package top view).

Updated Figure 98: UFBGA176+25 - ball 10 x 10 mm, 0.65 mm pitch

ultra thin fine pitch ball grid array package outline and Table 118:

UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball

grid array package mechanical data.

19-Jan-2018

Updated Arm wordmark and added Arm logo in Section 2: Description.

Updated LDC-TFT feature on cover page.

Updated Table 24: Typical and maximum current consumption in Run

mode, code with data processing running from Flash memory (ART

accelerator enabled except prefetch) or RAM and Table 26: Typical and

maximum current consumption in Sleep mode.

RADC minimum value added in Table 74: ADC characteristics.

LTDC clock output frequency changed to 83 MHz in Table 107: LTDC

characteristics.

Table 125. Document revision history

Date

Revision

Changes

STM32F427AI 数据表(PDF) 238 Page - STMicroelectronics

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