M39432 datasheet(10/28 Pages) STMICROELECTRONICS

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M39432

10/28

Program cycles, and after the sixth pulse on the W

line for Erase cycles.

Error flag, DQ5 (Flash memory block only).

This bit is set to ’1’ when there is a failure during a

Program, Sector Erase, or the Bulk Erase

instruction in the Flash memory block. Otherwise,

the bit is held at ‘0’.

If an error occurs during a Program or Sector

Erase instruction, the sector in which the error

occurred, must not be used any more. Other

sectors may still be used, though. The Error bit is

reset after a Reset instruction.

If DQ5 becomes set to ’1’ during either of the

polling algorithm, shown in Figure 4 and Figure 5,

DQ7 (DQ6) should be checked again in case it had

changed simultaneously with DQ5. If DQ7 shows

the original data bit (after a Program cycle) or if

DQ7 is set to ’1’ (after an Erase cycle), or if DQ6

has ceased to toggle, the operation is successful

and the calling routine can resume normal

execution. It is recommended, as a final check,

that a second Read be performed, and that the

read value be compared against the original data

(in the case of a Write or Program cycle) or against

the value FFh (in the case of an Erase cycle). If the

comparison shows false, this should be flagged as

an error.

Erase Time-Out Bit (DQ3). The Erase Time-Out

Bit can be used to identify the start of the internal

controller operation during a Sector Erase cycle.

While the sector addresses (after cycle 5 in Table

4) are being supplied at a faster rate than one

every 80

µs between two sector addresses, the

M39432 holds the DQ3 bit at 0. This indicates that

additional sectors can still be added to the list of

sectors that are to be erased. Once the internal

controller starts erasing, the Erase Timer Bit is set

to ‘1’.

BYTE WRITE (OR PAGE WRITE) IN EEPROM

Writing a byte, or a page of bytes, to the EEPROM

block is performed as an operation (see Table 3).

This is as opposed to Programming a byte in the

Flash

memory,

which

performed

instruction (see Table 4).

Byte Write in the EEPROM Block

A write operation is initiated when EE is taken low,

while EF is kept high, the Write Enable (W) is

taken low, and the output enable (G) is held high.

Addresses are latched on the falling edge of W or

EE (whichever occurs the later).

Once initiated, the Write operation continues

under internal timing, until it is completed. This

period (tWHRH) is specified in Table 16.

The status of the Write operation is indicated on

the Data Polling and Toggle bits (as described on

the previous page), and on the Ready/Busy output

(which is driven low for the duration of the internal

Write cycle).

Page Write in the EEPROM Block

The Page Write mode allows up to 64 bytes to be

written on a single page in a single go. This is

achieved through a series of successive Write

operations, no two of which are separated by more

than the tWLWL value (as specified in Table 16).

The page write is initiated as a byte write

operation: following the first Byte Write instruction,

the host may send another address and data with

a minimum data transfer rate of: 1/tWLWL. The

internal write cycle can start at any instant after

tWLWL. Once initiated, the write operation is

internally timed, and continues, uninterrupted,

until completion.

Figure 7. EEPROM SDP-Disable Flowchart

AI01699C

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 80h in

Address 5555h

Unprotected State

after

tWC (Write Cycle time)

Write AAh in

Address 5555h

Write 55h in

Address 2AAAh

Write 20h in

Address 5555h

Page Write

Timing

Table 8. Write the EEPROM Block Identifier

Other Address Lines

DQ0 - DQ7

VIH

VIL

VIH

VIL

VID

Don’t Care

64 user-defined bytes

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