M39432 datasheet(11/28 Pages) STMICROELECTRONICS

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M39432

All bytes must be located on the same page

address (A6-A18 must be the same for all bytes).

Otherwise, the Page Write operation is not

executed.

As with the single byte Write operation, described

above, the DQ6 and DQ7 lines can be used to

detect the beginning and end of the internally

controlled phase of the Page Write cycle.

EEPROM Block Software Data Protection

The Software Data Protection (SDP) instruction

protects the EEPROM block from inadvertent

Write operations, for example that might be

caused under uncontrolled bus conditions.

By default, the M39432 is shipped in the

unprotected state: the EEPROM memory can be

written

normally.

After

the

SDP Enable

instruction, the device enters the Protected Mode,

and further write operations have no effect on the

EEPROM contents.

The device remains in this mode until a valid SDP

Disable instruction has been received. The device

then returns to its unprotected state.

To enable the Software Data Protection, the

device has to be written (under Page Write timing

conditions) with three specific data bytes at three

specific memory locations (each location on a

different page) as shown in Table 4 and Figure 6.

Figure 6 shows that there are three ways to use

the SDP-Enable instruction. Firstly, as shown in

the flow-chart on the left, it can be used as a three-

byte instruction that sets the SDP. Secondly, it can

be used as a way of writing data to the EEPROM

even when the SDP is set. Only if the data to be

written is preceeded by the correct three byte

instruction, and all the bytes are written with the

correct Page Write timing, will the request be

accepted, and acted on. Lastly, if the SDP is

currently not set, the instruction can be used as a

means of performing a Page Write, and setting the

SDP at the same time.

To disable the Software Data Protection the user

has to write specific data bytes into six different

locations (under Page Write timing conditions)

with different bytes being written on different

pages, as shown in Figure 7.

The Software Data Protection state is held

internally in a non-volatile latch (and so the state is

remembered across power-on and power-off

events. Access to this latch, through the SDP

Enable and Disable instructions, require the same

write time (tWC) as for the non-volatile memory.

This Write operation can be monitored on the

Toggle bit (status bit DQ6) and the Ready/Busy

pin, but not on DQ7. The Ready/Busy output is

driven low from the first written byte (the first Write

AAh,@5555h of the SDP sequence) until the

completion of the internal Page Write sequence.

Writing the OTP Row

Writing in the OTP row is enabled by an instruction

composed of three specific Write operations,

under Page Write timing conditions, as shown in

Table 4. These instructions write data bytes at

three specific memory locations, each location on

a different page, followed by the data (between 1

and 64 bytes) that is to be stored in the OTP row.

This action can only be performed once. Even by

writing fewer than all 64 bytes on the first write to

the OTP row, none of the bytes, including any that

have not yet been changed, can be modified at a

later time.

When accessing the OTP row, the only least

significant address bits (A0 to A6) are decoded. Of

these, A6 must be held at 0.

Writing the EEPROM Block Identifier

The EEPROM Block Identifier (64 bytes) can be

written with a single Write operation with VID

applied on A9, and A6 is driven low, as shown in

Table 8.

Programming the Flash Block

Programming a byte in the Flash memory block is

performed using the instruction shown in Table 4.

This is different to writing data to the EEPROM

block, which is performed as an operation (as

shown in Table 3). Similarly, an instruction is

needed when erasing a sector of Flash memory.

The Program instruction is a sequence of three

specific Write operations, followed by a Write

operation bearing the address and data that is to

be written (as shown in Table 4). The M39432

automatically

starts

and

performs

the

programming after the fourth write operation. In

this way, the Flash memory block can be

programmed a byte at a time.

The Flash memory block rejects any further

instructions that arrive during the execution of the

Program instruction. During programming, the

memory status may be checked by reading the

status bits DQ7, DQ6 and DQ5, as described on

page 8.

Data Polling using DQ7. Please

see

the

description on page 8.

Data Toggling using DQ6. Please

see

the

description on page 8.

Flash Block Erase

A Write to the EEPROM block is an operation that

triggers an automatic, internal sequence of Byte

Erase followed by Byte Write.

The Flash memory block, though, is different.

Writing to the Flash memory block first requires an

explicit Erase operation.

The Flash memory Erase instruction cannot be

addressed to a byte at a time. The Erase can only

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