M39432 datasheet(6/28 Pages) STMICROELECTRONICS

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M39432

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To access these, A9 is held at VID (as specified in

Table 11) and the specific logic levels, shown in

Table 5, are applied to the address inputs A0, A1

and A6.

The OTP row is accessed with a specific software

sequence, as described in the section entitled

“Writing the OTP Row” on page 11.

Instructions

Instructions consist of a sequence of specific Write

operations, as summarized in Table 4. The time

between two consecutive bytes must be shorter

than the time-out value (tWLWL).

Each received byte is decoded sequentially, and

not executed as a standard Write operation. The

overall instruction is executed when the correct

number of bytes have been properly received.

The sequence must be followed exactly. If an

invalid combination of instruction bytes occurs, or

time-out between two consecutive bytes, the

device logic resets itself to the Read state, when

addressing the Flash block, or is directly decoded

as a single operation, when addressing the

EEPROM block.

The M39432 instructions set, as summarized in

Table 4, includes:

Program a byte in the Flash memory block

Read the Protection Status of a Flash Sector

Erase instructions:

– Flash Sector Erase

– Flash Block Erase

– Flash Sector Erase Suspend

– Flash Sector Erase Resume

EEPROM Power Down

Deep Power Down

Change the EEPROM software write protection:

– Enable SDP

–Disable SDP

OTP row access:

– Write the whole OTP row (once)

– Read from the OTP row

Reset and Return

Read identifiers:

– Read the Manufacturer Identifier

– Read the Flash Block Identifier

For efficiency, each instruction consists of a two-

byte escape sequence, followed by a command

byte or a confirmation byte. The escape sequence

consists of writing the value AAh at address

5555h, in the first cycle, and the value 55h at

address 2AAAh, in the second cycle.

In the case of the Erase instructions, an additional

escape sequence is required, for final confirmation

that the instruction is the intended one.

POWER SUPPLY AND CURRENT

CONSUMPTION

Power Up

The M39432 internal logic is reset, to Read mode,

upon a power-up event. All Write operations to the

EEPROM are inhibited for the first 5 ms.

No new Write cycles can be started when VCC is

below VLKO (as specified in Table 11). However,

for maximum security of the contents of the

memory, and to remove the possibility of a byte

being written on the first rising edge of EF, EE or

W, at least one of EF, EE or W should be tied to

VIH during the power-up process.

Stand-by

When both EE and EF are high, the memory

enters Stand-by mode, and the Data Input/Output

pins are placed in the high-impedance state. To

reduce the Supply Current to the Stand-by Supply

Current, EE and EF should be held within

VCC±0.2V.

If the Stand-by mode is set during a Program or

Erase cycle, the memory continues to use the

Supply Current until the cycle is complete.

Table 5. Device Identifier Operations

Note: 1. X = Don’t Care.

Instruction

Other Address

Lines

DQ0 - DQ7

Read Manufacturer

Identifier

VIL

VIH

VIL

VIH

VIL

VID

Don’t Care

20h

Read Flash Block

Identifier

VIL

VIH

VIL

VIH

VIL

VID

Don’t Care

0E3h

Read EEPROM

Block Identifier

VIH

VIL

VIH

VIL

VID

Don’t Care

64 user-

defined bytes

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