M50FW080 datasheet(17/56 Pages) STMICROELECTRONICS

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M50FW080

Bus operations

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Bus operations

The two interfaces have similar bus operations but the signals and timings are completely

different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality

of the part is available through this interface. Only a subset of functions are available

through the Address/Address Multiplexed (A/A Mux) Interface.

See the sections: The Firmware Hub (FWH) bus operations and Address/Address

Multiplexed (A/A Mux) bus operations, for details of the bus operations on each interface.

3.1

Firmware Hub (FWH) bus operations

The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control

line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data

corruption can be achieved using two further signals (TBL and WP). Finally two reset

signals (RP and INIT) are available to put the memory into a known state.

The data signals, control signal and clock are designed to be compatible with PCI electrical

specifications. The interface operates with clock speeds up to 33MHz.

The following operations can be performed using the appropriate bus cycles: Bus Read, Bus

Write, Standby, Reset and Block Protection.

3.1.1

Bus Read

Bus Read operations read from the memory cells, specific registers in the Command

Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input

Communication Frame, FWH4, is Low, VIL, as Clock rises and the correct Start cycle is on

FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select,

Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync

data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.

See Table 4 and Figure 6, for a description of the Field definitions for each clock cycle of the

transfer. See Table 22 and Figure 11, for details on the timings of the signals.

3.1.2

Bus Write

Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid

Bus Write operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock

rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host

will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7

on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.

See Table 5 and Figure 7, for a description of the Field definitions for each clock cycle of the

transfer. See Table 22 and Figure 11, for details on the timings of the signals.

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